In accordance with one embodiment of the present invention, an apparatus is disclosed. Device includes a memory array having a plurality of memory cells. Device is connected to the memory array, the memory access circuit configured to perform a write operation in response to a control signal, further comprising. Device is connected to the memory access circuit, at least in part, it is configured to apply a set of write parameters according to the number of write operations performed by the memory access circuit, according to a series of write parameters plurality to perform the memory cell write operation, further comprising a further configured control logic to provide a control signal to the memory access circuit.
.FIELD 1B