Invention Patent
- Patent Title: N-CHANNEL MOS INTEGRATED CIRCUIT DEVICE
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Application No.: JP14318083Application Date: 1983-08-03
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Publication No.: JPS6032357APublication Date: 1985-02-19
- Inventor: SAKIYAMA KEIZOU , NAKANO AKIHIKO , OKAYAMA MORIYA
- Applicant: SHARP KK
- Assignee: SHARP KK
- Current Assignee: SHARP KK
- Priority: JP14318083 1983-08-03
- Main IPC: H01L21/70
- IPC: H01L21/70 ; H01L21/8234 ; H01L27/088 ; H01L27/10 ; H01L27/108 ; H01L29/78
Abstract:
PURPOSE:To obtain an integrated circuit which is improved for the reliability at the operating time by using a substrate structure ready in its manufacture by forming the substrate for associating an N-channel MOSFET by altering the surface of an N type silicon substrate to P type. CONSTITUTION:An N type silicon layer 2 is formed on one surface of an N type silicon substrate 1, and a P type region 3 is then formed on the surface of the silicon layer 2. The region 3 is formed by inverting the conductive type over part or the entire surface of the layer 2. The layer 2 is formed by epitaxial growing, and the region 3 is formed by introducing P type impurity to the surface layer by thermal diffusing. The N type impurity is introduced into the region 3 to form source and drain region, and a gate insulating film and a gate electrode are then, formed, thereby forming a D-RAM made of N-MOSFET.
Public/Granted literature
- JPH0226542Y2 Public/Granted day:1990-07-19
Information query
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