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    3.
    发明专利
    失效

    公开(公告)号：JP2002530890A

    公开(公告)日：2002-09-17

    申请号：JP2000584527

    申请日：1999-11-23

    IPC: H01L21/302 ,  C09G1/02 ,  C09K3/14 ,  H01L21/02 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/70 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105

    Abstract: An integrated circuit structures formed by chemical mechanical polishing (CMP) process, which comprises a conductive pathway recessed in a dielectric substrate, wherein the conductive pathway comprises conductive transmission lines encapsulated in a transmission-enhancement material, and wherein the conductive pathway is filled sequentially by a first layer of the transmission-enhancement material followed by the conductive transmission line; a second layer of transmission-enhancement material encapsulating the conductive transmission line and contacting the first layer of the transmission-enhancement material, wherein the transmission-enhancement material is selected from the group consisting of high magnetic permeability material and high permittivity material. Such integrated circuit structure may comprise a device structure selected from the group consisting of capacitors, inductors, and resistors. Preferably, the transmission-enhancement material comprises MgMn ferrites, MgMnAl ferrites, barium strontium titanate, lead zirconium titanate, titanium oxide, tantalum oxide, etc.

    6.
    发明专利
    失效

    公开(公告)号：JP3254007B2

    公开(公告)日：2002-02-04

    申请号：JP17488392

    申请日：1992-06-09

    IPC: H01L27/12 ,  H01L21/336 ,  H01L21/70 ,  H01L21/77 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/01 ,  H01L27/092 ,  H01L29/417 ,  H01L29/78 ,  H01L29/786

    Abstract: In a field effect type device having a thin film-like active layer, there is provided a thin film-like semiconductor device including a top side gate electrode on the active layer and a bottom side gate electrode connected to a static potential, the bottom side gate electrode being provided between the active layer and a substrate. The bottom side gate electrode may be electrically connected to only one of a source and a drain of the field effect type device. Also, the production methods therefor are disclosed.

    MANUFACTURING METHOD FOR SEMICONDUCTOR ELECTRONIC ELEMENT
    7.
    发明专利
    MANUFACTURING METHOD FOR SEMICONDUCTOR ELECTRONIC ELEMENT 失效

    公开(公告)号：JP2001274463A

    公开(公告)日：2001-10-05

    申请号：JP2001043956

    申请日：2001-02-20

    Applicant: VISHAY SEMICONDUCTOR GMBH

    Inventor： MUEHLECK PETER

    IPC: H01L21/56 ,  H01L21/70 ,  H01L25/075 ,  H01L25/16 ,  H01L33/48 ,  H01L33/54 ,  H01L33/62 ,  H01L33/00

    Abstract: PROBLEM TO BE SOLVED: To solve the problem that a semiconductor electronic element is relatively large in a conventional manufacturing method so a printed board for a structure is required, and bonding is required on the front surface of the printed board from its rear surface. SOLUTION: A manufacturing method for a semiconductor electronic element (10) for surface mounting is provided, which comprises a process where a conductor board is prepared, a process where a semiconductor chip is fixed on a first surface of the conductor board, a process where an electric connection is formed between the semiconductor chip and the first surface of the conductor board, a process where a housing body is formed by sealing the electric connection with the semiconductor chip using an insulating material, and a process where the conductor boards (1; 11) is separated from a second surface (1.2) opposite to the first surface so that terminal regions (5, 5.1, 5.2) electrically insulated from each other are formed. This method is suitable for manufacturing a light source of a display panel, a back lighting of liquid-crystal display device, a light-emitting element used as an optical switch, as well as, a diode, a transistor, and active and passive electronic elements of integrated circuits.

    LAYOUT DESIGN METHOD
    8.
    发明专利
    LAYOUT DESIGN METHOD 失效

    公开(公告)号：JP2001210716A

    公开(公告)日：2001-08-03

    申请号：JP2000015985

    申请日：2000-01-25

    Applicant: NIPPON ELECTRIC IC MICROCOMPUT

    Inventor： NAGAYOSHI FUTOSHI ,  SATO SHOICHIRO

    IPC: H01L21/70 ,  G06F17/50 ,  H01L21/3205 ,  H01L21/82 ,  H01L23/485 ,  H01L23/52

    Abstract: PROBLEM TO BE SOLVED: To provide a layout design method which minimally deteriorates wiring while reducing damage to a gate insulting film by an antenna effect to an irreducible minimum. SOLUTION: A layout design method comprises an antenna effect suppressing process S20, which includes at least a first process P1 in which the area of each of wiring layers of a continuous metal wiring equipped with a first end connected to the gate electrodes of MOS Trs and a second end connected to the diffusion layers is calculated for each gage electrode respectively resting on first layout data second process P2 in which a first gate electrode is extracted, third process P3 in which it is checked whether a first connection wiring is present or not, forth process P4 in which it is checked whether a second connection wiring is present or not, fifth process P5 in which it is checked whether a third connection wiring is present or not, and sixth process P6 in which a wiring pattern is modified so as to connect the first gate electrode to the third connection wiring through a second wiring layer located above the first wiring layer.

    SEMICONDUCTOR DEVICE OF CHIP-ON-CHIP STRUCTURE
    10.
    发明专利
    SEMICONDUCTOR DEVICE OF CHIP-ON-CHIP STRUCTURE 失效

    公开(公告)号：JP2001094037A

    公开(公告)日：2001-04-06

    申请号：JP26574199

    申请日：1999-09-20

    Applicant: ROHM CO LTD

    Inventor： UEDA SHIGEYUKI

    IPC: H01L25/18 ,  H01L21/60 ,  H01L21/70 ,  H01L25/065 ,  H01L25/07

    Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device, which can be tested for confirming the function of each semiconductor chip element and for confirming only the connecting state of a first semiconductor chip and a second semiconductor chip etc., even after the first semiconductor chip and the second semiconductor chip are jointed. SOLUTION: In each bump BM of a master chip 1, an extending part 14 drawn out from the bump BM to the outside of a junction region 12 is formed long integrally with the bump. That is, the bump BM of the master chip 1 is formed long in a state bridging the boundary part of the junction region 12. Thereby, after the master chip 1 and a subordinate chip 2 are jointed, the operation confirmation of only the master chip 1 or the subordinate chip 2 and the connection confirmation of the master chip 1 and the subordinate chip 2 are enabled, by pressing test probes P against the parts of the extending part 14 which is drawn out to the outside of the junction region 12.

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