本发明提供一种使用真实及互补双比特线及双二元存储组件单元架构之电子内存,其包含一具有四个二元存储组件之内存单元对,每一内存单元对能够存在于多达十六种电子内存状态中。视允许的噪声边限(noise margin)及比特宽度选择而定,通常用以存储两个真实及互补数据比特之四个二元存储组件一起用以存储二、三或四个数据比特。该内存可为铁电内存FeRAM、一闪存、一ROM(唯读内存)、一动态内存DRAM、一OUM(相变化内存)、一MRAM(磁电阻随机存取内存)、一NAND内存或一NOR内存。

An electronic memory using true and complementary dual bit lines and dual binary storage elements cell architecture comprising a memory cell pair with four binary storage elements with each memory cell pair capable of existing in up to sixteen electronic memory states. The four binary storage elements together, normally used to store two true and complementary data bits, are used to store two, three, or four data bits depending on the noise margin allowed and bit width selection. The memory can be ferroelectric memory FeRAM, a flash memory, a ROM, a dynamic memory DRAM, an OUM, a MRAM, a NAND memory, or a NOR memory.