本发明揭露一种芯片承载器及芯片封装结构。芯片承载器包含可挠性基材层、第一引脚、第二引脚、第一以及第二测试垫。可挠性基材层包含功能区、芯片接合区、第一以及第二测试垫区。第一测试垫区设置于功能区之二相对侧边,且第一测试垫相邻排列于第一测试垫区内。第一引脚由芯片接合区内延伸至第一测试垫区内分别连接第一测试垫。第二测试垫区设置于第一测试垫区外侧,较第一测试垫区远离功能区,且第二测试垫相邻排列于第二测试垫区内。此外,第二引脚由芯片接合区内延伸经过第一测试垫区至第二测试垫区内分别连接第二测试垫。

The invention discloses a chip carrier which includes a flexible substrate, a plurality of first leads, a plurality of second leads, a plurality of first test pads, and a plurality of second test pads. The flexible substrate has a functional region, a chip-bonding region, at least two first test pad areas, and at least one second test pad area defined thereon. The first test pad areas are disposed aside the opposite sides of the functional region, and the first test pads are arranged in the first test pad areas. The first leads are elongated from the chip-bonding region to the first test pad areas, and each of the first leads is connected to the corresponding first test pad. The second test pad area is disposed outside the first test pad area and located relatively further from the functional region, and the second test pads are arranged in the second test pad area. Furthermore, the second leads are elongated from the chip-bonding region through the first test pad area to the second test pad area, and each of the second leads is connected to the corresponding second test pad.