本发明之目的在于提供一种亦可混载于电路构造微细化之接合耐压较低之电路组件之非挥发性半导体记忆设备。 于记忆单元1a中，第1深井DW1及第2深井DW2未相互限制，对于第1深井DW1及第2深井DW2，可将第1井W1之电容晶体管3a、3b、或第2井W2之写入晶体管4a、4b之动作所需之电压分别个别地施加于第1深井DW1及第2深井DW2。借此，于记忆单元1a中，因可使第1深井DW1与第1井W1之电压差、或第2深井DW2与第2井W2之电压差小于产生穿隧效应之电压差(18[V])，故依此可减小第1深井DW1及第1井W1间之接合电压、或第2深井DW2及第2井W2间之接合电压，如此亦可混载于电路构造微细化之接合耐压较低之电路组件。

Proposed is a nonvolatile semiconductor storage device, wherein with respect to a first deep well (DW1) and a second deep well (DW2) in a memory unit (1a), voltages required for operations of capacitive transistors (3a, 3b) of a first well (W1) and write transistors (4a, 4b) of a second well (W2) are individually applied to the first deep well (DW1) and the second deep well (DW2) without the first deep well (DW1) and the second deep well (DW2) being bound to each other, consequently, since in the memory unit, the voltage difference between the first deep well (DW1) and the first well (W1) and the voltage difference between the second deep well (DW2) and the second well (W2) can be made smaller than a voltage difference (18 [V]) generated by a tunnel effect, the junction voltage between the first deep well (DW1) and the first well (W1) and the junction voltage between the second deep well (DW2) and the second well (W2) can be lowered correspondingly, and therefore the nonvolatile semiconductor storage device can be mounted even in a circuit element having low junction withstand voltage and a miniaturized circuit structure.