本发明披露一种封装上封装构件,包含一底部封装以及一叠设于该底部封装上的顶部封装。底部封装包含一重布线层结构、至少一晶粒,设于该重布线层结构上并且被一成型模料包覆、复数个位于该晶粒中的穿硅通孔(TSVs)、复数个沿着该晶粒周边设置的穿模通孔(TMVs),以及复数个焊锡凸块或锡球。其中各该穿模通孔的孔径大于各该穿硅通孔的孔径。顶部封装是经由该穿硅通孔(TSVs)与该穿模通孔(TMVs)与该底部封装电连接。

A package-on-package (PoP) assembly includes a bottom die package and a top die package. The bottom die package includes an RDL structure, a die mounted on the RDL structure, a molding compound surrounding the chip, a plurality of through silicon vias (TSVs) in the die, a plurality of through mold vias (TMVs) around the die, and a plurality of solder bumps or solder balls. Each of the TMVs has a diameter that is greater than that of each of the TSVs. The top die package is electrically connected to the bottom die package through the TSVs and the TMVs.