An Integrated Circuit device, the device including: a base wafer including a single crystal layer, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between the plurality of first transistors, where the base wafer includes a memory bit-cell array including the first transistors and control bit-lines and word-lines; and a second layer including a plurality of second transistors, the second layer overlying the at least one metal layer, where the second layer includes a connecting via to the bit-lines or the word-lines, the connecting via has a diameter of less than 200 nm, and where the second layer includes control circuits to control the memory bit-cell array, the control circuits include the second transistors.