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    3D SEMICONDUCTOR DEVICE, STRUCTURE AND METHODS WITH MEMORY ARRAYS AND CONNECTIVITY STRUCTURES
    1.
    发明申请
    3D SEMICONDUCTOR DEVICE, STRUCTURE AND METHODS WITH MEMORY ARRAYS AND CONNECTIVITY STRUCTURES 有权

    公开(公告)号：US20250040141A1

    公开(公告)日：2025-01-30

    申请号：US18739083

    申请日：2024-06-10

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist ,  Eli Lusky

    IPC: H10B43/40 ,  H10B43/20 ,  H10B43/30 ,  H10B43/50

    Abstract: A 3D semiconductor device including dicing including an etch process; and including: a first level including a single crystal layer, and a memory control circuit which includes first transistors; a first metal layer overlaying the first single crystal layer; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; second transistors—which may include a metal gate—disposed atop the third metal layer; third transistors disposed atop the second transistors; a fourth metal layer disposed atop the third transistors; a memory array including word-lines and at least four memory mini arrays (each mini array includes at least four rows by four columns of memory cells), each memory cell includes at least one second transistor or at least one third transistor; and a connection path from fourth metal to third metal, the path includes a via disposed through the memory array.

    3D semiconductor device and structure with logic circuits and memory cells
    2.
    发明授权
    3D semiconductor device and structure with logic circuits and memory cells 有权

    公开(公告)号：US12183699B2

    公开(公告)日：2024-12-31

    申请号：US18106484

    申请日：2023-02-07

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

    IPC: H01L23/00 ,  H01L23/473 ,  H01L23/66 ,  H01L25/16 ,  H10B80/00

    Abstract: A 3D semiconductor device comprising: a first level; and a second level, wherein said first level comprises single crystal silicon and a plurality of logic circuits, wherein said plurality of logic circuits each comprise first transistors, wherein said second level is disposed above said first level and comprises a plurality of arrays of memory cells, said second level comprises a plurality of second transistors, wherein each of said memory cells comprises at least one of said second transistors, wherein said first level is bonded to said second level, wherein said bonded comprises regions of oxide to oxide bonds, wherein said bonded comprises regions of metal to metal bonds; and a thermal isolation layer disposed between said first level and said second level, wherein said thermal isolation layer provides a greater than 20° C. differential temperature between said first level and said second level during nominal operation of said device.

    3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH LOGIC CIRCUITS, MEMORY CELLS, AND PROCESSOR ARRAY
    3.
    发明申请
    3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH LOGIC CIRCUITS, MEMORY CELLS, AND PROCESSOR ARRAY 有权

    公开(公告)号：US20240389366A1

    公开(公告)日：2024-11-21

    申请号：US18786372

    申请日：2024-07-26

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

    IPC: H10B80/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

    Abstract: An integrated semiconductor device including: a first level; a second level, where the first level includes single crystal silicon and a plurality of logic circuits, where the plurality of logic circuits each include first transistors, where the second level is disposed above the first level and includes a plurality of arrays of first memory cells, where the second level includes second transistors, where each of the first memory cells includes at least one of the second transistors, where the first level is bonded to the second level; an array of processors; and a third level, where the third level includes third transistors, where the third level is disposed above the second level and includes a plurality of arrays of second memory cells, where each of the second memory cells includes at least one of the third transistors, where the device includes a substrate area greater than 1,000 mm2.

    3D memory semiconductor device and structure
    4.
    发明授权
    3D memory semiconductor device and structure 有权

    公开(公告)号：US12114494B2

    公开(公告)日：2024-10-08

    申请号：US17461075

    申请日：2021-08-30

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Eli Lusky

    IPC: H10B41/27 ,  H10B43/27

    CPC classification number: H10B41/27 ,  H10B43/27

    Abstract: A 3D memory device, the device including: a first vertical pillar, the first vertical pillar includes a transistor source; a second vertical pillar, the second vertical pillar includes the transistor drain, where the first vertical pillar and the second vertical pillar each functions as a source or functions as a drain for a plurality of overlaying horizontally-oriented memory transistors, where at least of one of the plurality of overlaying horizontally-oriented memory transistors is disposed between the first vertical pillar and the second vertical pillar, where the plurality of overlaying horizontally-oriented memory transistors are self-aligned being formed following a same lithography step, and where the first vertical pillar includes metal.

    3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH BONDING AND MEMORY CELLS
    7.
    发明公开
    3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH BONDING AND MEMORY CELLS 审中-公开

    公开(公告)号：US20240315059A1

    公开(公告)日：2024-09-19

    申请号：US18677553

    申请日：2024-05-29

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

    IPC: H10B80/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

    CPC classification number: H10B80/00 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/1436

    Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; a first metal layer; a second metal layer overlaying the first metal layer; and a second level including a plurality of second transistors and at least one third metal layer, where the second level overlays the first level, where at least one of the second transistors includes a transistor channel, where the second level includes a plurality of memory cells, where each of the plurality of memory cells includes at least one of the second transistors, where the device includes at least one Phase-Lock-Loop (“PLL”) circuit or at least one Digital-Lock-Loop (“DLL”) circuit, where the second level is directly bonded to the first level, and where the bonded includes metal to metal bonds.

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