Invention Grant
- Patent Title: Apparatus and method for inhibiting roundoff error in a floating point argument reduction operation
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Application No.: US15140739Application Date: 2016-04-28
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Publication No.: US10019232B2Publication Date: 2018-07-10
- Inventor: Jørn Nystad
- Applicant: ARM LIMITED
- Applicant Address: GB Cambridge
- Assignee: ARM Limited
- Current Assignee: ARM Limited
- Current Assignee Address: GB Cambridge
- Agency: Nixon & Vanderhye P.C.
- Priority: GB1510452.4 20150615
- Main IPC: G06F7/483
- IPC: G06F7/483 ; G06F7/499

Abstract:
An apparatus and method are provided for inhibiting roundoff error in a floating point argument reduction operation. The apparatus has reciprocal estimation circuitry that is responsive to a first floating point value to determine a second floating point value that is an estimated reciprocal of the first floating point value. During this determination, the second floating point value has both its magnitude and its error bound constrained in dependence on a specified value N. Argument reduction circuitry then performs an argument reduction operation using the first and second floating point values as inputs, in order to generate a third floating point value. The use of the specified value N to constrain both the magnitude and the error bound of the second floating point value causes roundoff error to be inhibited in the third floating point value that is generated by the argument reduction operation. This enables such an argument reduction operation to be used as part of a more complex computation, such as a logarithm computation, with the inhibiting of roundoff error in the argument reduction result allowing the overall result to exhibit small relative error across the whole representable input range.
Public/Granted literature
- US20160364209A1 APPARATUS AND METHOD FOR INHIBITING ROUNDOFF ERROR IN A FLOATING POINT ARGUMENT REDUCTION OPERATION Public/Granted day:2016-12-15
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