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公开(公告)号：US11982735B2
公开(公告)日：2024-05-14
申请号：US16992949
申请日：2020-08-13
申请人： RavenOPS, Inc.
CPC分类号： G01S13/91 , G01S13/66 , G06F7/483 , G06F7/49936 , G06T1/20 , G06T15/005 , G06F9/3877 , G06F9/544
摘要： High speed scrubbing of airspace radar returns is provided. A system can include a central processing unit (“CPU”) and a graphical processing unit (“GPU”). The CPU loads time-ordered airspace radar return data that includes radar returns each encoded as an object with location information, time information, and property information. The GPU generates arrays including the location information, the time information, and the property information reorganized into a location array, a time array, and a property-based array. The GPU receives an indication to scrub a display of at least a portion of the airspace radar return data to a time window prior to a current display time or subsequent to the current display time. The GPU retrieves, from the arrays, a location entry and a property-based entry that satisfy the time window. The GPU renders frames with pixels corresponding to the location entry, the time entry, and the property-based entry.
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公开(公告)号：US20240103806A1
公开(公告)日：2024-03-28
申请号：US18533372
申请日：2023-12-08
发明人： Joseph Bates
IPC分类号： G06F7/483 , G06F7/38 , G06F7/523 , H03K19/17728
CPC分类号： G06F7/483 , G06F7/38 , G06F7/4833 , G06F7/5235 , H03K19/17728
摘要： A processor or other device, such as a programmable and/or massively parallel processor or other device, includes processing elements designed to perform arithmetic operations (possibly but not necessarily including, for example, one or more of addition, multiplication, subtraction, and division) on numerical values of low precision but high dynamic range (“LPHDR arithmetic”). Such a processor or other device may, for example, be implemented on a single chip. Whether or not implemented on a single chip, the number of LPHDR arithmetic elements in the processor or other device in certain embodiments of the present invention significantly exceeds (e.g., by at least 20 more than three times) the number of arithmetic elements, if any, in the processor or other device which are designed to perform high dynamic range arithmetic of traditional precision (such as 32 bit or 64 bit floating point arithmetic).
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公开(公告)号：US11907719B2
公开(公告)日：2024-02-20
申请号：US16914009
申请日：2020-06-26
申请人： Intel Corporation
IPC分类号： G06F9/30 , G06N20/00 , G06F30/343 , G06F30/34 , G06F30/38 , G06F7/50 , G06F7/523 , H03K19/17748 , H03M7/24 , G06F7/556 , H03K19/177 , G06F7/483
CPC分类号： G06F9/30101 , G06F7/50 , G06F7/523 , G06F7/556 , G06F9/30105 , G06F30/34 , G06F30/343 , G06F30/38 , G06N20/00 , H03K19/177 , H03K19/17748 , H03M7/24 , G06F7/483
摘要： The present disclosure describes a digital signal processing (DSP) block that includes a plurality of columns of weight registers and a plurality of inputs configured to receive a first plurality of values and a second plurality of values. The first plurality of values is stored in the plurality of columns of weight registers after being received. Additionally, the DSP block includes a plurality of multipliers configured to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.
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公开(公告)号：US11900242B2
公开(公告)日：2024-02-13
申请号：US17688853
申请日：2022-03-07
发明人： Shaoli Liu , Xinkai Song , Bingrui Wang , Yao Zhang , Shuai Hu
IPC分类号： G06N3/063 , G06N3/04 , G06F7/483 , G06F7/544 , G06N3/06 , G06N3/08 , G06F17/15 , G06F17/16 , H01L25/065
CPC分类号： G06N3/063 , G06F7/483 , G06F7/5443 , G06F17/153 , G06F17/16 , G06N3/04 , G06N3/06 , G06N3/08 , H01L25/065 , G06F2207/4824
摘要： Provided are an integrated circuit chip apparatus and a related product, the integrated circuit chip apparatus being used for executing a multiplication operation, a convolution operation or a training operation of a neural network. The present technical solution has the advantages of a small amount of calculation and low power consumption.
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公开(公告)号：US11900241B2
公开(公告)日：2024-02-13
申请号：US17688844
申请日：2022-03-07
发明人： Shaoli Liu , Xinkai Song , Bingrui Wang , Yao Zhang , Shuai Hu
IPC分类号： G06N3/063 , G06N3/04 , G06F7/483 , G06F7/544 , G06N3/06 , G06N3/08 , G06F17/15 , G06F17/16 , H01L25/065
CPC分类号： G06N3/063 , G06F7/483 , G06F7/5443 , G06F17/153 , G06F17/16 , G06N3/04 , G06N3/06 , G06N3/08 , H01L25/065 , G06F2207/4824
摘要： Provided are an integrated circuit chip apparatus and a related product, the integrated circuit chip apparatus being used for executing a multiplication operation, a convolution operation or a training operation of a neural network. The present technical solution has the advantages of a small amount of calculation and low power consumption.
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公开(公告)号：US20230409285A1
公开(公告)日：2023-12-21
申请号：US18035226
申请日：2021-11-03
申请人： Lemurian Labs Inc.
IPC分类号： G06F7/483 , G06N3/0464 , G06N3/08
CPC分类号： G06F7/4833 , G06N3/0464 , G06N3/08
摘要： Methods and apparatus are described for the use of a multi-dimensional logarithmic number system for hardware acceleration of inner product computations. These methods and apparatus may be used for any device that requires low-power, low-area and fast inner product computational units, such as, for example, deep neural network training and inference calculations on edge devices. In a particular embodiment, neural network training is performed using multi-dimensional logarithmic data representation, to obtain a set of neural network weight coefficients. Given the determined weight coefficients, the second base is optimized for multi-dimensional logarithmic data representation. This optimal representation may be used to perform inference by the neural network.
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公开(公告)号：US11842129B1
公开(公告)日：2023-12-12
申请号：US16886602
申请日：2020-05-28
申请人： X Development LLC
IPC分类号： G06F30/23 , G06N3/08 , G06F7/483 , G06F111/10
CPC分类号： G06F30/23 , G06F7/483 , G06N3/08 , G06F2111/10
摘要： Methods, systems, and apparatus, including computer programs encoded on computer storage media, for correcting finite floating-point numerical simulation and optimization. Defining a loss function within a simulation space composed of a plurality of voxels each having an initial degree of freedom, the simulation space encompassing one or more interfaces of the component; defining an initial structure for the one or more interfaces in the simulation space; calculating, using a computer system with a finite floating-point precision, values for an electromagnetic field at each voxel using a finite-difference time domain solver to solve Maxwell's equations; and determining, for each voxel, whether to increase a respective numerical precision of respective values representing behavior of the electromagnetic field at the voxel above a threshold precision by the computer system and, in response, assigning one or more additional degrees of freedom to the voxel.
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公开(公告)号：US20230376313A1
公开(公告)日：2023-11-23
申请号：US17747919
申请日：2022-05-18
申请人： Intel Corporation
CPC分类号： G06F9/30145 , G06F9/30021 , G06F7/22 , G06F7/483
摘要： Techniques for instructions for min-max operations are described. An example apparatus comprises decoder circuitry to decode a single instruction, the single instruction to include fields for identifiers of a first source operand, a second source operand, an a destination operand, a field for an immediate operand, and a field for an opcode, the opcode to indicate execution circuitry is to perform a min-max operation, and execution circuitry to execute the decoded instruction according to the opcode to perform the min-max operation to determine a particular operation of five or more minimum and maximum operations in accordance with a value of the immediate operand, perform the determined particular operation on the identified first source operand and the identified second source operand to return a result, and store the result into the identified destination operand. Other examples are described and claimed.
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公开(公告)号：US11822899B2
公开(公告)日：2023-11-21
申请号：US16689907
申请日：2019-11-20
发明人： Ray Bittner , Alessandro Forin
CPC分类号： G06F7/483 , G06F5/012 , G06F7/52 , G06F7/5443 , G06F17/16 , G06N3/063 , G06N3/084 , G06N3/044
摘要： Apparatus and methods are disclosed for performing block floating-point (BFP) operations, including in implementations of neural networks. All or a portion of one or more matrices or vectors can share one or more common exponents. Techniques are disclosed for selecting the shared common exponents. In some examples of the disclosed technology, a method includes producing BFP representations of matrices or vectors, at least two elements of the respective matrices or vectors sharing a common exponent, performing a mathematical operation on two or more of the plurality of matrices or vectors, and producing an output matrix or vector. Based on the output matrix or vector, one or more updated common exponents are selected, and an updated matrix or vector is produced having some elements that share the updated common exponents.
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公开(公告)号：US20230367548A1
公开(公告)日：2023-11-16
申请号：US18320524
申请日：2023-05-19
发明人： Peng WU , Jian OUYANG
摘要： A computing method is provided. The computing method includes: obtaining a plurality of first fixed point numbers and a plurality of first exponents that correspond to the plurality of first floating point numbers, and a plurality of second fixed point numbers and a plurality of second exponents that correspond to the plurality of second floating point numbers; obtaining a fixed point product of each of the plurality of first fixed point numbers and a second fixed point number corresponding to the first fixed point number, and a corresponding fixed point product exponent; obtaining a fixed point inner product calculation result of the first vector and the second vector; and obtaining, based on the fixed point inner product calculation result, a floating point inner product calculation result in a floating point data format corresponding to the fixed point inner product calculation result.
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