Methods and systems for improved matching for on-chip capacitors may comprise in a semiconductor die comprising an on-chip capacitor with one or more metal layers: electrically coupling a first set of metal fingers, electrically coupling a second set of metal fingers that are interdigitated with the first set of metal fingers, wherein the first set of metal fingers and the second set of metal fingers are arranged symmetrically in the semiconductor die, and configuring the on-chip capacitor in a plurality of symmetric sections, wherein a boundary between each of the plurality of sections is configured in a zig-zag pattern. The first set of metal fingers and the second set of metal fingers may be arranged with radial symmetry. A first set of metal fingers in a first metal layer may be electrically coupled to a set of metal fingers in a second metal layer.