Invention Grant
- Patent Title: Short-resistant chip-scale package
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Application No.: US15261444Application Date: 2016-09-09
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Publication No.: US10020335B2Publication Date: 2018-07-10
- Inventor: Wei-Chih Chien , Ying-Chih Kuo
- Applicant: OmniVision Technologies, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: OmniVision Technologies, Inc.
- Current Assignee: OmniVision Technologies, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Lathrop Gage LLP
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L21/44 ; H01L27/146

Abstract:
A short-resistant CSP includes an isolation layer, an electrically conductive RDL, and an insulating layer. The electrically conductive RDL is on the isolation layer and includes a first and a second RDL segment. The insulating layer includes a first insulator portion between the isolation layer and the first RDL segment to improve electrical isolation between the first and second RDL segments. A method for preventing short-circuiting between conductors of CSP includes (1) depositing a first insulating layer on a first substrate region, (2) depositing a RDL segment on the substrate above the first substrate region, at least a portion of the first insulating layer being between the first RDL segment and the first substrate region, and (3) depositing a second RDL segment on the substrate above a second substrate region, such that the first insulating layer interrupts a leakage current path between the first and second RDL segments.
Public/Granted literature
- US20180076248A1 SHORT-RESISTANT CHIP-SCALE PACKAGE Public/Granted day:2018-03-15
Information query
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