Invention Grant
- Patent Title: Sequential circuit with error detection
-
Application No.: US15422392Application Date: 2017-02-01
-
Publication No.: US10024916B2Publication Date: 2018-07-17
- Inventor: Keith A. Bowman , James W. Tschanz , Nam Sung Kim , Janice C. Lee , Christopher B. Wilkerson , Shih-Lien L. Lu , Tanay Karnik , Vivek K. De
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Womble Bond Dickinson (US) LLP
- Main IPC: G01R31/3177
- IPC: G01R31/3177 ; G01R31/317

Abstract:
Sequential circuits with error-detection are provided. They may, for example, be used to replace traditional master-slave flip-flops, e.g., in critical path circuits to detect and initiate correction of late transitions at the input of the sequential. In some embodiments, such sequentials may comprise a transition detector with a time borrowing latch.
Public/Granted literature
- US20170139006A1 SEQUENTIAL CIRCUIT WITH ERROR DETECTION Public/Granted day:2017-05-18
Information query