公开(公告)号：US09819266B2

公开(公告)日：2017-11-14

申请号：US14757732

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Vaibhav Vaidya ,  Vivek K. De ,  Krishnan Ravichandran

IPC: H02M3/158

CPC classification number: H02M3/158 ,  H02M1/083 ,  H02M3/1588 ,  Y02B70/1466

Abstract: Generally, this disclosure describes an apparatus. The apparatus includes switch controller circuitry and zero crossing logic circuitry. The switch controller circuitry is to control a conduction state of a high side switch and a low side switch in a DC to DC converter. The zero crossing logic circuitry includes phase comparator circuitry, a first clocking circuitry and a second clocking circuitry. Each clocking circuitry includes one or more delay elements. The zero crossing logic circuitry is to monitor a switch node voltage, Vsw, and to determine whether Vsw is greater than a reference, Vref. The switch controller circuitry is to turn off a low side switch if Vsw is greater than Vref while the low side switch is turned on, Vsw greater than Vref corresponding to a negative inductor current.

公开(公告)号：US09772903B2

公开(公告)日：2017-09-26

申请号：US15083122

申请日：2016-03-28

Applicant: INTEL CORPORATION

Inventor： Jaydeep P. Kulkarni ,  Keith A. Bowman ,  James W. Tschanz ,  Vivek K. De

IPC: G06F11/10 ,  G06F11/00 ,  G11C29/52 ,  G06F9/30 ,  G06F11/07 ,  G06F9/38 ,  G11C29/42 ,  G11C7/18

CPC classification number: G06F11/1068 ,  G06F9/30141 ,  G06F9/3861 ,  G06F11/0751 ,  G06F11/1008 ,  G11C7/18 ,  G11C29/42 ,  G11C29/52

Abstract: The disclosed system and method detect and correct register file read path errors that may occur as a result of reducing or eliminating supply voltage guardbands and/or frequency guardbands for a CPU, thereby increasing overall energy efficiency of the system.

公开(公告)号：US09520877B2

公开(公告)日：2016-12-13

申请号：US14572031

申请日：2014-12-16

Applicant: Intel Corporation

Inventor： Pascal A. Meinerzhagen ,  Sandip Kundu ,  James W. Tschanz ,  Vivek K. De

IPC: H03L7/00 ,  H03K19/003 ,  H03K5/26

CPC classification number: H03K19/00323 ,  H03K5/26

Abstract: Described are apparatuses and methods for detecting or repairing minimum-delay errors. The apparatus may include a minimum-delay error detector (MDED) to receive a clock signal and a data path signal and to detect a minimum-delay error (MDE) in the data path based on the received data path signal and the clock signal. The MDE may be repaired by adjusting one or more regional clock buffers coupled to the MDED. Further, the apparatus may include minimum-delay path replicas (MDPRs) used for detecting and repairing MDEs during normal system operations. Other embodiments may be described and/or claimed.

Abstract translation: 描述了用于检测或修复最小延迟误差的装置和方法。 该装置可以包括用于接收时钟信号和数据路径信号的最小延迟误差检测器（MDED），并且基于所接收的数据路径信号和时钟信号来检测数据路径中的最小延迟误差（MDE）。 可以通过调整耦合到MDED的一个或多个区域时钟缓冲器来修复MDE。 此外，该装置可以包括用于在正常系统操作期间检测和修复MDE的最小延迟路径副本（MDPR）。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20160182354A1

公开(公告)日：2016-06-23

申请号：US14579845

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Vivek K. De ,  Ram K. Krishnamurthy ,  Gregory K. Chen ,  Mark A. Anders ,  Himanshu Kaul

IPC: H04L12/727 ,  H04L12/26 ,  H04L12/933

CPC classification number: H04L45/121 ,  G06F15/7825 ,  H04L43/0852 ,  H04L45/125 ,  H04L45/24 ,  H04L45/60 ,  H04L49/109

Abstract: A router of a network-on-chip receives delay information associated with a plurality of links of the network-on-chip. The router determines at least one link of a data path based on the delay information.

Abstract translation: 片上网络的路由器接收与片上网络的多个链路相关联的延迟信息。 路由器基于延迟信息确定数据路径的至少一个链路。

公开(公告)号：US20220101625A1

公开(公告)日：2022-03-31

申请号：US17549583

申请日：2021-12-13

Applicant: Intel Corporation

Inventor： Sriram R. Vangal ,  Hyochan An ,  Vivek K. De ,  Narayan Srinivasa ,  Farzin G. Guilak ,  Miguel Bautista Gabriel ,  Pratik Dasharathkumar Patel

IPC: G06V10/774 ,  G06V10/74 ,  G06V10/771 ,  G06V10/22 ,  G11C29/42 ,  G11C29/12 ,  G06N3/04

Abstract: An integrated circuit (IC) is provided for in-situ anomaly detection. Sensors in the IC generates sensor datasets including information indicating conditions in the IC. A processing unit in the IC uses a sensor dataset and a model to detect and classify the anomaly. The processing unit may filter the sensor dataset, extract features from the filtered sensor dataset, and input the features into the model. The model outputs one or more classifications of the anomaly. A feature may be a distance vector that represents a difference between a data value in the filtered sensor dataset from a reference data value. The model may be a network of bit-cells in the IC. The model may be continuously trained in-situ, i.e., on the IC. The processing unit may provide the classifications to another processing unit in the IC. The other processing unit may mitigate the anomaly based on the classifications.

公开(公告)号：US10269419B2

公开(公告)日：2019-04-23

申请号：US15604519

申请日：2017-05-24

Applicant: Intel Corporation

Inventor： Jaydeep P. Kulkarni ,  Vivek K. De ,  Muhammad M. Khellah

IPC: G11C7/12 ,  G11C11/419

Abstract: Described is an apparatus which comprises: a memory bit-cell; a local bit-line (LBL) coupled to the memory bit-cell via a read port device; a NAND gate circuitry coupled to the LBL; and a stack of keepers coupled to the LBL, wherein at least one transistor of the stack of keepers is controllable according to an output of the NAND gate circuitry, wherein the stack of keepers includes transistors with variable strength which are to be turned on overtime.

公开(公告)号：US20190094931A1

公开(公告)日：2019-03-28

申请号：US15718991

申请日：2017-09-28

Applicant: INTEL CORPORATION

Inventor： Khondker Z. Ahmed ,  Vivek K. De ,  Nachiket V. Desai ,  Suhwan Kim ,  Harish K. Krishnamurthy ,  Xiaosen Liu ,  Turbo Majumder ,  Krishnan Ravichandran ,  Christopher Schaef ,  Vaibhav Vaidya ,  Sriram R. Vangal

IPC: G06F1/26 ,  G06N99/00

Abstract: Various embodiments of the invention may analyze previous patterns of harvested energy to predict future patterns of available harvested energy. This prediction may then be used to choose from among multiple methods of energy reduction techniques. The energy reduction techniques may include multiple versions of reducing or modifying instruction execution. Reduced instruction execution may include reducing the precision of various calculations.

公开(公告)号：US20180342289A1

公开(公告)日：2018-11-29

申请号：US15604519

申请日：2017-05-24

Applicant: Intel Corporation

Inventor： Jaydeep P. KULKARNI ,  Vivek K. De ,  Muhammad M. Khellah

IPC: G11C11/419

CPC classification number: G11C11/419

Abstract: Described is an apparatus which comprises: a memory bit-cell; a local bit-line (LBL) coupled to the memory bit-cell via a read port device; a NAND gate circuitry coupled to the LBL; and a stack of keepers coupled to the LBL, wherein at least one transistor of the stack of keepers is controllable according to an output of the NAND gate circuitry, wherein the stack of keepers includes transistors with variable strength which are to be turned on overtime.

公开(公告)号：US20170243637A1

公开(公告)日：2017-08-24

申请号：US15495954

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Jaydeep P. Kulkarni ,  Bibiche M. Geuskens ,  James Tschanz ,  Vivek K. De ,  Muhammed M. Khellah

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C5/145 ,  G11C5/147 ,  G11C5/148 ,  G11C7/12 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4074 ,  G11C11/412 ,  G11C11/417 ,  G11C11/418 ,  G11C13/0038 ,  G11C29/021 ,  G11C29/028 ,  G11C2207/2227

Abstract: Methods and systems to provide a multi-Vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted control to the logic block. A multi-Vcc environment may be implemented to isolate a Vmin-limiting logic block from a single-Vcc environment, such as to reduce Vmin and/or improve energy efficiency in the single-Vcc environment. The logic block may include bit cells of a register file, a low-level processor cache, and/or other memory system. A cell Vcc may be boosted during a read mode and/or write wordlines (WWLs) and/or read wordlines (RWLs) may be asserted with boost. A wordline decoder may include a voltage level shifter with differential split-level logic, and a dynamic NAND, which may include NAND logic, a keeper circuit, and logic to delay a keeper control based on a delay of the level shifter to reduce contention during an initial NAND evaluation phase.

公开(公告)号：US09722606B2

公开(公告)日：2017-08-01

申请号：US15331280

申请日：2016-10-21

Applicant: INTEL CORPORATION

Inventor： Arijit Raychowdhury ,  Charles Augustine ,  James W. Tschanz ,  Vivek K. De

IPC: G05F1/10 ,  G05F1/59 ,  H03K19/00 ,  G05F1/46 ,  G06F1/32 ,  H03K3/037

CPC classification number: H03K19/0016 ,  G05F1/10 ,  G05F1/461 ,  G05F1/59 ,  G06F1/3287 ,  G06F1/3296 ,  H03K3/0377 ,  H03K19/0008

Abstract: Described is an apparatus which comprises: a clamp coupled between a first power supply and a second power supply, the clamp including a plurality of transistors, a circuit to operate with the second power supply; and a control unit to turn on and off the plurality of transistors to adjust the second power supply when the apparatus enters a low power mode. The control unit includes a first comparator to compare the second power supply with a first reference, a second comparator to compare the second power supply with a second reference, and a counter. The counter counts up when the second power supply is higher than the first reference and counts down when the second power supply is lower than the second reference.