Invention Grant
- Patent Title: Wafer-level package having asynchronous FIFO buffer used to deal with data transfer between different dies and associated method
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Application No.: US15015145Application Date: 2016-02-04
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Publication No.: US10037293B2Publication Date: 2018-07-31
- Inventor: Yi-Hung Chen , Yuan-Chin Liu
- Applicant: MEDIATEK INC.
- Applicant Address: CN Hefei, Anhui
- Assignee: Nephos (Hefei) Co. Ltd.
- Current Assignee: Nephos (Hefei) Co. Ltd.
- Current Assignee Address: CN Hefei, Anhui
- Agent Winston Hsu
- Main IPC: G06F13/38
- IPC: G06F13/38 ; G06F13/362 ; G06F13/40 ; H04L7/00

Abstract:
A wafer-level package has a first die and a second die. The first die has a first clock source arranged to generate a first clock, a first sub-system arranged to generate transmit data, and an output circuit arranged to output the transmit data according to the first clock. The second die has a second sub-system, a second clock source arranged to generate a second clock, and an input circuit having an asynchronous first-in first-out (FIFO) buffer. The input circuit buffers the transmit data transferred from the output circuit in the asynchronous FIFO buffer according to the first clock, and outputs the buffered transmit data in the asynchronous FIFO buffer to the second sub-system according to the second clock.
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