公开(公告)号：US10037293B2

公开(公告)日：2018-07-31

申请号：US15015145

申请日：2016-02-04

Applicant: MEDIATEK INC.

Inventor： Yi-Hung Chen ,  Yuan-Chin Liu

IPC: G06F13/38 ,  G06F13/362 ,  G06F13/40 ,  H04L7/00

CPC classification number: G06F13/362 ,  G06F13/4022 ,  H04L7/00 ,  H04L7/0008 ,  H04L7/005

Abstract: A wafer-level package has a first die and a second die. The first die has a first clock source arranged to generate a first clock, a first sub-system arranged to generate transmit data, and an output circuit arranged to output the transmit data according to the first clock. The second die has a second sub-system, a second clock source arranged to generate a second clock, and an input circuit having an asynchronous first-in first-out (FIFO) buffer. The input circuit buffers the transmit data transferred from the output circuit in the asynchronous FIFO buffer according to the first clock, and outputs the buffered transmit data in the asynchronous FIFO buffer to the second sub-system according to the second clock.

公开(公告)号：US11387176B2

公开(公告)日：2022-07-12

申请号：US16813898

申请日：2020-03-10

Applicant: MEDIATEK INC.

Inventor： Tzu-Hung Lin ,  Yuan-Chin Liu

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a first semiconductor die, and a second semiconductor die. The substrate includes a first substrate partition and a second substrate partition. The first substrate partition has a first wiring structure. The second substrate partition is adjacent to the first substrate partition and has a second wiring structure. The first substrate partition and the second substrate partition are surrounded by a first molding material. The first semiconductor die is disposed over the substrate and electrically coupled to the first wiring structure. The second semiconductor die is disposed over the substrate and electrically coupled to the second wiring structure.

公开(公告)号：US20160240497A1

公开(公告)日：2016-08-18

申请号：US15015110

申请日：2016-02-03

Applicant: MEDIATEK INC.

Inventor： Yi-Hung Chen ,  Yuan-Chin Liu

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065

Abstract: A wafer-level package includes a plurality of dies and a plurality of connection paths. The dies include at least a first die and a second die. The dies are arranged in a side-by-side fashion, and a first side of the first die is adjacent to a first side of the second die. The connection paths connect input/output (I/O) pads arranged on the first side of the first die to I/O pads arranged on the first side of the second die, wherein adjacent I/O pads on the first side of the first die are connected to adjacent I/O pads on the first side of the second die via connection paths on only a single layer. For example, the first die is identical to the second die. For another example, the wafer-level package is an integrated fan-out (InFO) package or a chip on wafer on substrate (CoWoS) package. For yet another example, the dies are assembled in the wafer-level package to perform a network switch function.

Abstract translation: 晶片级封装包括多个管芯和多个连接路径。 模具包括至少第一模具和第二模具。 模具并排布置，第一模具的第一侧与第二模具的第一侧相邻。 连接路径将布置在第一管芯的第一侧上的输入/输出（I / O）焊盘连接到布置在第二管芯的第一侧上的I / O焊盘，其中在第一管芯的第一侧上的相邻I / O焊盘 管芯通过仅在单个层上的连接路径连接到第二管芯的第一侧上的相邻I / O焊盘。 例如，第一模具与第二模具相同。 另一个例子，晶圆级封装是集成扇出（InFO）封装或衬底上晶片上的芯片（CoWoS）封装。 对于另一示例，将晶片级封装中的芯片组装起来以执行网络切换功能。

公开(公告)号：US12002742B2

公开(公告)日：2024-06-04

申请号：US17838412

申请日：2022-06-13

Applicant: MEDIATEK INC.

Inventor： Tzu-Hung Lin ,  Yuan-Chin Liu

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/49816 ,  H01L23/3192 ,  H01L24/13 ,  H01L24/45 ,  H01L24/73 ,  H01L25/0655

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a first semiconductor die, and a second semiconductor die. The substrate includes a first substrate partition and a second substrate partition. The first substrate partition has a first wiring structure. The second substrate partition is adjacent to the first substrate partition and has a second wiring structure. The first substrate partition and the second substrate partition are surrounded by a first molding material. The first semiconductor die is disposed over the substrate and electrically coupled to the first wiring structure. The second semiconductor die is disposed over the substrate and electrically coupled to the second wiring structure.

公开(公告)号：US10515939B2

公开(公告)日：2019-12-24

申请号：US15015110

申请日：2016-02-03

Applicant: MEDIATEK INC.

Inventor： Yi-Hung Chen ,  Yuan-Chin Liu

IPC: H01L23/48 ,  H01L25/00 ,  H01L25/065 ,  H01L23/538

Abstract: A wafer-level package includes a plurality of dies and a plurality of connection paths. The dies include at least a first die and a second die. The dies are arranged in a side-by-side fashion, and a first side of the first die is adjacent to a first side of the second die. The connection paths connect input/output (I/O) pads arranged on the first side of the first die to I/O pads arranged on the first side of the second die, wherein adjacent I/O pads on the first side of the first die are connected to adjacent I/O pads on the first side of the second die via connection paths on only a single layer. For example, the first die is identical to the second die. For another example, the wafer-level package is an integrated fan-out (InFO) package or a chip on wafer on substrate (CoWoS) package. For yet another example, the dies are assembled in the wafer-level package to perform a network switch function.

公开(公告)号：US20160239444A1

公开(公告)日：2016-08-18

申请号：US15015145

申请日：2016-02-04

Applicant: MEDIATEK INC.

Inventor： Yi-Hung Chen ,  Yuan-Chin Liu

IPC: G06F13/362 ,  G06F1/06 ,  G06F13/40

CPC classification number: G06F13/362 ,  G06F13/4022 ,  H04L7/00 ,  H04L7/0008 ,  H04L7/005

Abstract: A wafer-level package has a first die and a second die. The first die has a first clock source arranged to generate a first clock, a first sub-system arranged to generate transmit data, and an output circuit arranged to output the transmit data according to the first clock. The second die has a second sub-system, a second clock source arranged to generate a second clock, and an input circuit having an asynchronous first-in first-out (FIFO) buffer. The input circuit buffers the transmit data transferred from the output circuit in the asynchronous FIFO buffer according to the first clock, and outputs the buffered transmit data in the asynchronous FIFO buffer to the second sub-system according to the second clock.

Abstract translation: 晶片级封装具有第一裸片和第二裸片。 第一管芯具有布置成产生第一时钟的第一时钟源，被布置为产生发送数据的第一子系统，以及布置成根据第一时钟输出发送数据的输出电路。 第二管芯具有第二子系统，布置成产生第二时钟的第二时钟源和具有异步先进先出（FIFO）缓冲器的输入电路。 输入电路根据第一时钟对从异步FIFO缓冲器中的输出电路传送的发送数据进行缓冲，并根据第二时钟将异步FIFO缓冲器中缓存的发送数据输出到第二子系统。