Invention Grant
- Patent Title: Method of manufacturing wafer level package and wafer level package manufactured thereby
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Application No.: US15405619Application Date: 2017-01-13
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Publication No.: US10050019B2Publication Date: 2018-08-14
- Inventor: Tae Hoon Kim , Jong Hoon Kim , Dae Won Kim , Hyeong Seok Choi
- Applicant: SK hynix Inc.
- Applicant Address: KR Icheon-si, Gyeonggi-do
- Assignee: SK hynix Inc.
- Current Assignee: SK hynix Inc.
- Current Assignee Address: KR Icheon-si, Gyeonggi-do
- Agency: William Park & Associates Ltd.
- Priority: KR10-2016-0080125 20160627
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L25/065 ; H01L21/56 ; H01L21/768 ; H01L23/29 ; H01L23/31 ; H01L23/00 ; H01L25/00

Abstract:
Provided are a wafer level package and a manufacturing method thereof. A reconfigured substrate may be formed by disposing a first semiconductor die on a dummy wafer, and forming a molding layer and a mold covering layer. A second semiconductor die may be stacked on the first semiconductor die and a photosensitive dielectric layer may be formed. Conductive vias penetrating the photosensitive dielectric layer may be plated.
Public/Granted literature
- US20170373041A1 METHOD OF MANUFACTURING WAFER LEVEL PACKAGE AND WAFER LEVEL PACKAGE MANUFACTURED THEREBY Public/Granted day:2017-12-28
Information query
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