公开(公告)号：US10109794B2

公开(公告)日：2018-10-23

申请号：US15634573

申请日：2017-06-27

Applicant: SK hynix Inc.

Inventor： Gyu Hyun Kim ,  Dae Won Kim ,  Byoung Ki Lee ,  Han Woo Cho

IPC: H01L45/00

Abstract: A method of semiconductor device fabrication that includes sequentially forming an interfacial conductive layer and an etch stop layer on a resistive memory layer; forming a main conductive layer on the etch stop layer; exposing a portion of the etch stop layer by patterning the main conductive layer; exposing a portion of the interfacial conductive layer by patterning the portion of the etch stop layer; forming an upper electrode structure by patterning the portion of the interfacial conductive layer; cleaning a surface of the upper electrode structure and an exposed surface of the resistive memory layer; and patterning the resistive memory layer using the upper electrode structure as an etch mask.

公开(公告)号：US09748481B2

公开(公告)日：2017-08-29

申请号：US14883216

申请日：2015-10-14

Applicant: SK hynix Inc.

Inventor： Gyu Hyun Kim ,  Dae Won Kim ,  Byoung Ki Lee ,  Han Woo Cho

IPC: H01L45/00

CPC classification number: H01L45/1675 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/16

Abstract: A method of semiconductor device fabrication that includes sequentially forming an interfacial conductive layer and an etch stop layer on a resistive memory layer; forming a main conductive layer on the etch stop layer; exposing a portion of the etch stop layer by patterning the main conductive layer; exposing a portion of the interfacial conductive layer by patterning the portion of the etch stop layer; forming an upper electrode structure by patterning the portion of the interfacial conductive layer; cleaning a surface of the upper electrode structure and an exposed surface of the resistive memory layer; and patterning the resistive memory layer using the upper electrode structure as an etch mask.

公开(公告)号：US20230380144A1

公开(公告)日：2023-11-23

申请号：US18105245

申请日：2023-02-03

Applicant: SK hynix Inc.

Inventor： Hae Jung PARK ,  Dae Won Kim ,  Young Chun Kim ,  Hyun Jin Lee ,  Jin Hwan Jeon ,  Ri Choi

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/315 ,  H10B12/34 ,  H10B12/485 ,  H10B12/02

Abstract: A semiconductor device includes: a semiconductor substrate; a plurality of bit line structures spaced apart from each other over the semiconductor substrate and each including a stacked structure of a bit line and a bit line hard mask; a contact pad positioned over the semiconductor substrate between the neighboring bit line structures; a contact structure including a stacked structure of a first contact formed over the contact pad and a second contact having a greater line width than the first contact; a first spacer structure interposed between the first contact and each of the bit line structures; and a second spacer structure interposed between the second contact and each of the bit line structures and having a smaller dielectric constant than the first spacer structure.

公开(公告)号：US12113107B2

公开(公告)日：2024-10-08

申请号：US17549328

申请日：2021-12-13

Applicant: SK hynix Inc.

Inventor： Dae Won Kim ,  Tae Kyun Kim ,  Dong Goo Choi

IPC: H01L29/40 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H10B12/00

CPC classification number: H01L29/401 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76834 ,  H10B12/09 ,  H10B12/482 ,  H10B12/485

Abstract: A method for fabricating a semiconductor device includes: forming an insulating layer over a substrate including a cell region and a peripheral region; forming an opening in the insulating layer by selectively etching the insulating layer in the cell region; forming a plug conductive layer to fill the opening and cover the insulating film; etching the plug conductive layer and the insulating layer in the peripheral region by using a peri-open mask covering the cell region; trimming the peri-open mask to expose the plug conductive layer in a boundary region where the cell region and the peripheral region contact each other; etching the plug conductive layer in the boundary region by using the trimmed peri-open mask; forming a peri-gate conductive layer over the entire surface of the substrate; and etching the peri-gate conductive layer by using a cell open mask.

公开(公告)号：US10050019B2

公开(公告)日：2018-08-14

申请号：US15405619

申请日：2017-01-13

Applicant: SK hynix Inc.

Inventor： Tae Hoon Kim ,  Jong Hoon Kim ,  Dae Won Kim ,  Hyeong Seok Choi

IPC: H01L23/48 ,  H01L25/065 ,  H01L21/56 ,  H01L21/768 ,  H01L23/29 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00

Abstract: Provided are a wafer level package and a manufacturing method thereof. A reconfigured substrate may be formed by disposing a first semiconductor die on a dummy wafer, and forming a molding layer and a mold covering layer. A second semiconductor die may be stacked on the first semiconductor die and a photosensitive dielectric layer may be formed. Conductive vias penetrating the photosensitive dielectric layer may be plated.