Methods and apparatuses regarding shared buffer arbitration for packet-based switching are described. A data packet may be received by a packet buffer including a first plurality of banks of memory units and a second plurality of banks of memory units. Each memory unit may store one cell of data and accommodate one access operation in one clock cycle. In an event that the data packet includes at least two cells of data, the at least two cells of the data packet may be alternately written into at least one memory unit in the first plurality of banks of memory units and at least one memory unit in the second plurality of banks of memory units. Cells of data packets may be read from the first plurality of banks of memory units and the second plurality of banks of memory units according to a time-division multiplexing (TDM) scheme.