- 专利标题： Interconnection for memory electrodes
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申请号： US15676700申请日： 2017-08-14
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公开(公告)号： US10056120B2公开(公告)日： 2018-08-21
- 发明人: Hernan A. Castro , Everardo Torres Flores , Stephen H. S. Tang
- 申请人： Micron Technology, Inc.
- 申请人地址： US ID Boise
- 专利权人： MICRON TECHNOLOGY, INC.
- 当前专利权人： MICRON TECHNOLOGY, INC.
- 当前专利权人地址： US ID Boise
- 代理机构： Holland & Hart LLP
- 主分类号： G11C5/06
- IPC分类号： G11C5/06 ; H01L27/24 ; H01L27/22 ; H01L45/00 ; H01L21/768 ; G11C8/08 ; G11C5/02 ; H01L27/02
摘要：
Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level.
公开/授权文献
- US20170352387A1 INTERCONNECTION FOR MEMORY ELECTRODES 公开/授权日：2017-12-07