Invention Grant
- Patent Title: Memory array and link error correction in a low power memory sub-system
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Application No.: US14859063Application Date: 2015-09-18
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Publication No.: US10061645B2Publication Date: 2018-08-28
- Inventor: Jungwon Suh , David Ian West
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Seyfarth Shaw LLP
- Main IPC: G06F11/10
- IPC: G06F11/10 ; G11C29/52

Abstract:
A method of memory array and link error correction in a low power memory sub-system includes embedding error correction code (ECC) parity bits within unused data mask bits during a normal write operation and during a read operation. The method also includes embedding the ECC parity bits in a mask write data byte corresponding to an asserted data mask bit during a mask write operation.
Public/Granted literature
- US20170004035A1 MEMORY ARRAY AND LINK ERROR CORRECTION IN A LOW POWER MEMORY SUB-SYSTEM Public/Granted day:2017-01-05
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