Apparatuses and method relating to DFE include a decision feedback equalizer with first and second integrating summers configured to receive an input differential signal. A bias current circuit is configured to alternate biasing of the first and second integrating summers. The first and second integrating summers alternately integrate, during clock signal phases of a clock signal and its complement, for transconductance of the input differential signal to a first output differential signal and a second output differential signal, respectively. The first and second integrating summers alternately drive, during other clock signal phases of the clock signal and its complement, residual voltages of the first output differential signal and the second output differential signal, respectively, to a same voltage level. A first clock signal and a second clock signal are out of phase with respect to one another for interleaving the first output differential signal and the second output differential signal.