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公开(公告)号：US11639962B1
公开(公告)日：2023-05-02
申请号：US17199874
申请日：2021-03-12
申请人： Xilinx, Inc.
IPC分类号： G01R31/3177 , G01R31/317 , G01R31/3185 , G01R31/3187 , G06F11/27
摘要： An integrated circuit (IC) can include a plurality of circuit blocks, wherein each circuit block includes design for testability (DFT) circuitry. The DFT circuitry can include a scan interface, wherein each scan interface is uniform with the scan interface of each other circuit block of the plurality of circuit blocks, an embedded deterministic test circuit coupled to the scan interface, wherein the embedded deterministic test circuit couples to circuitry under test, and a scan response analyzer coupled to the scan interface. The scan response analyzer is configured to operate in a selected scan response capture mode selected from a plurality of scan response capture modes. The IC can include a global scan router connected to the scan interfaces of the plurality of circuit blocks. The global scan router is configured to activate a subset of the plurality of circuit blocks in parallel for a scan test.
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公开(公告)号：US11630935B1
公开(公告)日：2023-04-18
申请号：US17498048
申请日：2021-10-11
申请人： Xilinx, Inc.
IPC分类号： G06F30/30 , G01R31/28 , G06F30/3308 , G06F30/323 , G01R31/3183
摘要： Computer-based simulation of a device under test (DUT) corresponding to a user circuit design includes providing an adapter configured to couple to the DUT during the computer-based simulation (simulation). The adapter is configured to translate incoming high-level programming language (HLPL) transactions into DUT compatible data for conveyance to the DUT and translate DUT compatible data generated by the DUT to outgoing HLPL transactions. A communication server is provided that couples to the adapter during the simulation. The communication server is configured to exchange the incoming and outgoing HLPL transactions with an entity executing external to the simulation. A communication layer client is provided that is configured to execute external to the simulation and exchange the incoming and outgoing HLPL transactions with the communication server. The communication layer client provides an application programming interface through which an external computer program generates data traffic to drive the DUT within the simulation.
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公开(公告)号：US11621808B1
公开(公告)日：2023-04-04
申请号：US16654460
申请日：2019-10-16
申请人： Xilinx, Inc.
发明人： Shuo Jiao , Romi Mayder , Bowen Li
摘要： Apparatus and associated methods relate to predicting various transient output waveforms at a receiver's output after an initial neural network model is trained by a receiver's transient input waveform and a corresponding transient output waveform. In an illustrative example, the machine learning model may include an adaptive-ordered auto-regressive moving average external input based on neural networks (NNARMAX) model designed to mimic the performance of a continuous time linear equalization (CTLE) mode of the receiver. A Pearson Correlation Coefficient (PCC) score may be determined to select numbers of previous inputs and previous outputs to be used in the neural network model. In other examples, corresponding bathtub characterizations and eye diagrams may be extracted from the predicted transient output waveforms. Providing a machine learning model may, for example, advantageously predict various data patterns without knowing features or parameters of the receiver or related channels.
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公开(公告)号：US20230096400A1
公开(公告)日：2023-03-30
申请号：US17485382
申请日：2021-09-25
申请人： Xilinx, Inc.
发明人： Sai Lalith Chaitanya Ambatipudi , Vamsi Krishna Nalluri , Sandeep Jayant Sathe , Chaithanya Dudha , Krishna Kishore Bhagavatula
IPC分类号： G06F7/50
摘要： An electronic system includes a mapping circuit configured to receive input samples of a dataset within a defined range of values. The mapping circuit is configured to perform comparisons that compare each input sample to each of a plurality of comparison values selected from the defined range of values. For each comparison, the mapping circuit generates an indication value specifying whether the input sample used in the comparison is greater than or equal to the comparison value used in the comparison. The system includes an adder circuit configured to generate a sum of the indication values for each comparison value and a memory configured to maintain counts corresponding to the comparison values. The counts are updated by the respective sums. The system includes a threshold detection circuit configured to determine, for the dataset, a threshold value or threshold range based on the counts read from the memory.
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公开(公告)号：US20230094315A1
公开(公告)日：2023-03-30
申请号：US17488112
申请日：2021-09-28
申请人： XILINX, INC.
发明人： Hongzhi ZHAO , Christophe ERDMANN
摘要： Embodiments herein describe adapting a PIM model to compensate for changing PIM interference. A PIM model can include circuitry that generates a PIM compensation value that compensates for (i.e., mitigates or subtracts) PIM interference caused by transmitting two or more transmitter (TX) carriers in the same path. The disclosed adaptive scheme generates updated coefficients for the PIM model which are calculated after the RX signal has been removed from the RX channel. In this manner, as the PIM interference changes due to environmental conditions (e.g., temperature at the base station), the adaptive scheme can update the PIM model to generate a PIM compensation value that cancels the PIM interference.
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公开(公告)号：US11615052B1
公开(公告)日：2023-03-28
申请号：US16420946
申请日：2019-05-23
申请人： Xilinx, Inc.
发明人： Rishi Surendran , Akella Sastry , Abnikant Singh
IPC分类号： G06F15/78 , G06F16/901 , G06F30/20 , H04L49/109 , H04L49/25
摘要： Some examples described herein relate to packet identification (ID) assignment for a routing network in a programmable integrated circuit (IC). In an example, a design system includes a processor and a memory coupled to the processor. The memory stores instruction code. The processor is configured to execute the instruction code to construct an interference graph based on routes of logical nets through switches in a routing network, and assign identifications to the routes comprising performing vertex coloring of vertices of the interference graph. The interference graph includes the vertices and interference edges. Each vertex represents one of the logical nets having a route. Each interference edge connects two vertices that represent corresponding two logical nets that have routes that share at least one port of a switch. The identifications correspond to values assigned to the vertices by the vertex coloring.
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公开(公告)号：US11606125B2
公开(公告)日：2023-03-14
申请号：US16964581
申请日：2019-01-30
申请人： XILINX, INC.
发明人： Volker Aue
摘要： The present invention provides a beamforming antenna (100, 200, 400) comprising a plurality of antenna elements (101, 102, 201, 202, 401, 402, 440), and a signal generator (103, 403) that is configured to generate for each one of the antenna elements (101, 102, 201, 202, 401, 402, 440) a calibration signal (106, 107, 206, 406, 335) for radiation by the respective antenna element (101, 102, 201, 202, 401, 402, 440) and to supply the generated calibration signals (106, 107, 206, 406, 335) to the respective antenna elements (101, 102, 201, 202, 401, 402, 440). Further, the present invention provides a measurement device (330, 430) for measuring properties (336) of a beamforming antenna (100, 200, 400) according to any one of the preceding claims via calibration signals (106, 107, 206, 406, 335) emitted by antenna elements (101, 102, 201, 202, 401, 402, 440) of the beamforming antenna (100, 200, 400), the measurement device (330, 430) comprising a measurement receiver (332) that is configured to receive an incoming signal (334) comprising the calibration signals (106, 107, 206, 406, 335), and a property determination module (333) that is coupled to the measurement receiver (332) and that is configured to determine the properties (336) of the beamforming antenna (100, 200, 400) based on the received calibration signals (106, 107, 206, 406, 335). Further, the present invention provides a respective antenna measurement system (450) and a respective method.
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公开(公告)号：US11605886B1
公开(公告)日：2023-03-14
申请号：US17133518
申请日：2020-12-23
申请人： XILINX, INC.
发明人： Gamal Refai-Ahmed , Chi-Yi Chao , Lik Tsang , Jens Weis , Brendan Farley , Anthony Torza , Suresh Ramalingam
IPC分类号： H01Q1/42 , H01L23/427 , H01Q1/02
摘要： An antenna assembly is provided having passive cooling elements that enable compact design. In one example, an antenna assembly is provided that includes a heat sink assembly having an interior side and an exterior side, an antenna array, an antenna circuit board, and a radome. The antenna circuit board includes at least one integrated circuit (IC) die. The IC die has a conductive primary heat dissipation path to the interior side of the heat sink assembly. The radome is coupled to the heat sink assembly and encloses the antenna circuit board and the antenna array between the radome and the heat sink assembly. The heat sink assembly includes a metal base plate and at least a first heat pipe embedded with the metal base plate. The first heat pipe is disposed between the metal base plate and the IC die.
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9.发明授权公开(公告)号：US11593547B1
公开(公告)日：2023-02-28
申请号：US17411484
申请日：2021-08-25
申请人： Xilinx, Inc.
IPC分类号： G06F30/392 , G06F30/31 , G06F30/347 , G06F30/34 , G06F111/04
摘要： Predicting performance of a circuit design includes determining memory access patterns of kernels of the circuit design for implementation in an integrated circuit (IC) and generating a plurality of different floorplans. Each floorplan specifies a mapping of memory interfaces of the kernels to memories of the selected IC and an allocation of the kernels to a plurality of programmable pattern generator (PPG) circuit blocks of a circuit architecture implemented in the IC. The plurality of different floorplans are executed using the circuit architecture in the IC. The plurality of PPG circuit blocks mimic the memory access patterns of the kernels for each of the plurality of different floorplans during the executing. One or more design constraints are generated based on a selected floorplan. The selected floorplan is selected from the plurality of different floorplans based on one or more performance metrics determined from the executing.
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公开(公告)号：US20230055704A1
公开(公告)日：2023-02-23
申请号：US17408218
申请日：2021-08-20
申请人： Xilinx, Inc.
发明人： Sebastian Turullols , Kyle Corbett , Sudipto Chakraborty , Siva Santosh Kumar Pyla , Ravinder Sharma , Kaustuv Manji , Jayaram PVSS , Stephen P. Rozum , Ch Vamshi Krishna , Susheel Puthana
IPC分类号： G06F30/392 , G06F30/3953 , G06F30/398
摘要： Using a flat shell for an accelerator card includes reading a flat shell from one or more computer readable storage media using computer hardware, wherein the flat shell is a synthesized, unplaced, and unrouted top-level circuit design specifying platform circuitry. A kernel specifying user circuitry is synthesized using the computer hardware. The kernel is obtained from the one or more computer readable storage media. The synthesized kernel is linked, using the computer hardware, to the flat shell forming a unified circuit design. The unified circuit design is placed and routed, using the computer hardware, to generate a placed and routed circuit design specifying the platform circuitry and the user circuitry for implementation in an integrated circuit.
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