An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a replica radial distribution element, a bit lag control element, and a synchronous lag receiver. The replica radial distribution element is configured to receive a first signal, and is configured to generate a second signal, where the replica radial distribution element comprises replicated propagation path lengths, loads, and buffering of a radial distribution network for a strobe. The bit lag control element is configured to measure a propagation time beginning with assertion of the first signal and ending with assertion of the second signal, and is configured to generate a value on a lag bus that indicates the propagation time. The bit lag control element has delay lock control and a gray encoder. The delay lock control is configured to select one of a plurality of successively delayed versions of the first signal that coincides with the assertion of the second signal, where the delay lock control selects the one of a plurality of successively delayed versions of the first signal by incrementing and decrementing bus states of select inputs on a first mux, and where the plurality of successively delayed versions of the first signal comprises inputs to the first mux, and where the plurality of successively delayed versions comprises outputs of a first plurality of series-coupled matched inverter pairs. The gray encoder is configured to gray encode the propagation time to generate the value on the lag bus. The synchronous lag receiver is configured to receive one of a plurality of radially distributed strobes and a data bit, and is configured to delay registering of the data bit by the propagation time. The synchronous lag receiver includes a second plurality of series-coupled matched inverter pairs, a second mux, and a bit receiver. The second plurality of series-coupled matched inverter pairs is configured to generate successively delayed versions of the data bit. The second mux is coupled to the second plurality of series-coupled matched inverter pairs, is configured to receive the value on the lag bus, and is configured to select one of the successively delayed versions of the data bit that corresponds to the value. The bit receiver is configured to receive the one of the successively delayed versions of the data bit and one of a plurality of radially distributed strobe signals, and is configured to register the state of the one of the successively delayed versions of the data bit upon assertion of the one of a plurality of radially distributed strobe signals.