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19241 条记录 (耗时 0.043 秒)

    UNIFIED CONTROLLER SYSTEM FOR POINT-OF-SALE DEVICES
    1.
    发明公开
    UNIFIED CONTROLLER SYSTEM FOR POINT-OF-SALE DEVICES 审中-公开

    公开(公告)号：US20240362605A1

    公开(公告)日：2024-10-31

    申请号：US18139153

    申请日：2023-04-25

    申请人： FCS Processing, LLC

    发明人： Jeff WAUGHTAL ,  David Avery

    IPC分类号： G06Q20/20 ,  G06F13/38 ,  G06F13/42 ,  G06K7/00 ,  G06K7/08 ,  G06K7/10

    CPC分类号： G06Q20/208 ,  G06F13/382 ,  G06F13/4282 ,  G06K7/0008 ,  G06K7/087 ,  G06K7/10297 ,  G06F2213/0042

    摘要： Disclosed are various aspects of a point-of-sale system, such aspects may include a computing device encased in a weather resistant shell and electronically connected to peripheral components through a controller board. The controller board may be located in a first void region of the weather resistant shell to allow protection of the electrical components from the elements. A point-of-sale system may include a power supply, wherein the power supply is in electrical connection with the controller board and in a second void region of the weather resistant shell. A point-of-sale system may include a payment device, having an EMV chip card reader, a magnetic stripe card reader, a near field communication (“NFC”) reader, wherein the payment device is in electrical communication with the controller board and in a third void region of the weather resistant shell. A point-of-sale system may also include a wireless radio module in electrical communication with the controller board and in a fourth void region of the weather resistant shell.

    Communication device and communication system
    5.
    发明授权
    Communication device and communication system 有权

    公开(公告)号：US12130768B2

    公开(公告)日：2024-10-29

    申请号：US17927249

    申请日：2021-06-04

    申请人： Sony Semiconductor Solutions Corporation

    发明人： Junya Yamada ,  Satoshi Ota ,  Toshihisa Hyakudai

    IPC分类号： H04L1/16 ,  G06F13/42 ,  H04L1/1607

    CPC分类号： G06F13/4282 ,  H04L1/1607

    摘要： Communication devices and systems are disclosed. In one example, a communication device includes a LINK that performs protocol conversion of a signal from a Master and outputs the converted signal to a Slave SerDes, and of a signal from the Slave SerDes and outputs the converted signal to the Master. The LINK alternatively selects a first mode and a second mode. In the first mode, the LINK converts a 1-byte signal transmitted from the Master into a signal of a first communication standard in units of the 1-byte signal and transmits the converted signal to the Slave SerDes, then receives a signal of the first communication standard including an ACK signal representing an acknowledgement or a NACK signal representing a negative acknowledgement, and converts the received signal into a signal of a second communication standard and transmits the converted signal to the Master.

    Closed chassis debugging through tunneling
    6.
    发明授权
    Closed chassis debugging through tunneling 有权

    公开(公告)号：US12130724B2

    公开(公告)日：2024-10-29

    申请号：US16912545

    申请日：2020-06-25

    申请人： Intel Corporation

    发明人： Gilad Shayevitz ,  Tsvika Kurts ,  Vladislav Kopzon ,  Reuven Rozic ,  Yaniv Hayat

    IPC分类号： G06F11/36 ,  G06F11/34 ,  G06F13/38 ,  G06F13/42

    CPC分类号： G06F11/3636 ,  G06F11/3476 ,  G06F11/3688 ,  G06F11/3692 ,  G06F13/385 ,  G06F13/4282

    摘要： A system can include a host machine connected to a device under test (DUT) by a serial link. The host machine can include a serial interface, such as a Thunderbolt interface, and a memory. The DUT can include a trace data source, a high-speed trace interface (HTI) to receive trace data from the trace data source, a serial interface (such as a Thunderbolt interface), and a PIPE interface connecting the HTI with the serial interface. The HTI is to send the trace data to the serial interface through the PIPE interface. The serial interface is to packetize the trace data into a conforming packet format, and send the trace data as a packet across the serial link to the host machine. The host machine can receive the trace data at the host-side serial interface, store the trace data in memory, and process the trace data for debugging the DUT.

    DYNAMIC DIE-TO-DIE SERIAL LANE CONFIGURATION
    8.
    发明公开
    DYNAMIC DIE-TO-DIE SERIAL LANE CONFIGURATION 审中-公开

    公开(公告)号：US20240354275A1

    公开(公告)日：2024-10-24

    申请号：US18302535

    申请日：2023-04-18

    申请人： QUALCOMM INCORPORATED

    发明人： Kunal DESAI ,  Deepak Kumar AGARWAL

    IPC分类号： G06F13/42 ,  G06F11/07

    CPC分类号： G06F13/4282 ,  G06F11/0745 ,  G06F11/076

    摘要： A die-to-die serial data link may be dynamically configured to exclude lanes associated with data errors. In a test mode, data may be transmitted from a first die to a second die over lanes of the link. In the second die, data received on the link in the test mode may be compared with an expected data pattern to detect any bit mismatches. When there are no more than a threshold number of mismatched bits, a receive path in the second die may be configured to use all of the lanes. When there are more than the threshold number of mismatched bits, a sub-group of the lanes that are not associated with mismatched bits may be determined, and the receive path in the second die may be configured to use the sub-group of lanes. In the first die, a transmit path may be configured to use the sub-group of lanes.

    Transaction card with integrated USB device
    10.
    发明授权
    Transaction card with integrated USB device 有权

    公开(公告)号：US12125015B2

    公开(公告)日：2024-10-22

    申请号：US18382352

    申请日：2023-10-20

    申请人： Capital One Services, LLC

    发明人： Timur Sherif ,  Matthew Kloster ,  Tao Lin ,  Kevin Osborn

    IPC分类号： G06Q20/20 ,  G06F13/42 ,  G06Q20/38

    CPC分类号： G06Q20/204 ,  G06F13/4282 ,  G06Q20/382 ,  G06F2213/0042

    摘要： A transaction card is provided for communicating with a computing device. The transaction card may comprise a computer interface device, at least one memory, at least one processor, and a card reader module. The card reader module configured to receive, from the computing device through the computer interface device, a first data packet comprising a request associated with a transaction, the first data packet being compatible with an interface protocol. The card reader module may process the first data packet to generate a second data packet compatible with the payment authentication protocol; provide the second data packet to the processor; receive, from the processor, a third data packet comprising a response to the request; process the third data packet to generate a fourth data packet based on the response, the fourth data packet compatible with the interface protocol; and transmit, to the computer interface device, the fourth data packet.