- 专利标题: Using direct sums and invariance groups to test partially symmetric quantum-logic circuits
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申请号: US15194645申请日: 2016-06-28
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公开(公告)号: US10082539B2公开(公告)日: 2018-09-25
- 发明人: Pawel Jasionowski
- 申请人: International Business Machines Corporation
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理机构: Schmeiser, Olsen & Watts, LLP
- 代理商 John Pivnichny
- 主分类号: G01R31/00
- IPC分类号: G01R31/00 ; G01R31/3177 ; G06N99/00 ; G06F17/16 ; G06F17/11 ; H03K19/00 ; H03K19/0175
摘要:
A method and associated systems for using direct sums and invariance groups to optimize the testing of partially symmetric quantum-logic circuits is disclosed. A test system receives information that describes the architecture of a quantum-logic circuit to be tested. The system uses this information to organize the circuit's inputs into two or more mutually exclusive subsets of inputs. The system computes a direct sum of a set of groups associated with the subsets in order to generate an invariance group that contains one or more invariant permutations of the circuit's inputs. These invariant permutations can be used to reduce the number of tests required to fully verify the circuit for all possible input vectors. Once one specific input vector has been verified, there is no need to test other vectors that can be generated by performing any one of the invariant permutations upon the previously verified vector.
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