Invention Grant
- Patent Title: Semiconductor package structure and semiconductor process
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Application No.: US15208569Application Date: 2016-07-12
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Publication No.: US10083902B2Publication Date: 2018-09-25
- Inventor: Yuan-Chang Su , Chih-Cheng Lee , Cheng-Lin Ho
- Applicant: Advanced Semiconductor Engineering, Inc.
- Applicant Address: TW Kaosiung
- Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- Current Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- Current Assignee Address: TW Kaosiung
- Agency: Foley & Lardner LLP
- Agent Cliff Z. Liu
- Main IPC: H01L23/498
- IPC: H01L23/498 ; H05K1/18 ; H01L21/48

Abstract:
Disclosed is a semiconductor package structure and manufacturing method. The semiconductor package structure includes a first dielectric layer, a second dielectric layer, a component, a patterned conductive layer and at least two conductive vias. The first dielectric layer has a first surface and a second surface opposite the first surface. The second dielectric layer has a first surface and a second surface opposite the first surface. The second surface of the first dielectric layer is attached to the first surface of the second dielectric layer. A component within the second dielectric layer has at least two electrical contacts adjacent to the second surface of the first dielectric layer. The patterned conductive layer within the first dielectric layer is adjacent to the first surface of the first dielectric layer. The conductive vias penetrate the first dielectric layer and electrically connect the electrical contacts with the patterned conductive layer.
Public/Granted literature
- US20160322292A1 SEMICONDUCTOR PACKAGE STRUCTURE AND SEMICONDUCTOR PROCESS Public/Granted day:2016-11-03
Information query
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