- 专利标题： Vector multiplication with accumulation in large register space
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申请号： US13538523申请日： 2012-06-29
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公开(公告)号： US10095516B2公开(公告)日： 2018-10-09
- 发明人: Shay Gueron , Vlad Krasnov , Robert Valentine , Zeev Sperber , Amit Gradstein , Simon Rubanovich
- 申请人： Shay Gueron , Vlad Krasnov , Robert Valentine , Zeev Sperber , Amit Gradstein , Simon Rubanovich
- 申请人地址： US CA Santa Clara
- 专利权人： INTEL CORPORATION
- 当前专利权人： INTEL CORPORATION
- 当前专利权人地址： US CA Santa Clara
- 代理机构： Nicholson De Vos Webster & Elliott LLP
- 主分类号： G06F9/30
- IPC分类号： G06F9/30 ; G06F7/52 ; G06F9/38
摘要：
An apparatus is described having an instruction execution pipeline that has a vector functional unit to support a vector multiply add instruction. The vector multiply add instruction to multiply respective K bit elements of two vectors and accumulate a portion of each of their respective products with another respective input operand in an X bit accumulator, where X is greater than K.
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