Invention Grant
- Patent Title: Semiconductor integrated circuit device having an ESD protection circuit
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Application No.: US15835340Application Date: 2017-12-07
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Publication No.: US10096593B2Publication Date: 2018-10-09
- Inventor: Shiro Usami
- Applicant: Socionext Inc.
- Applicant Address: JP Kanagawa
- Assignee: SOCIONEXT INC.
- Current Assignee: SOCIONEXT INC.
- Current Assignee Address: JP Kanagawa
- Agency: McDermott Will & Emery LLP
- Priority: JP2011-202824 20110916
- Main IPC: H01L23/52
- IPC: H01L23/52 ; H01L27/02 ; H01L23/528 ; H01L29/87

Abstract:
Diffusion regions having the same conductivity type are arranged on a side of a second wiring and a side of a third wiring, respectively under a first wiring connected to a signal terminal. Diffusion regions are separated in a whole part or one part of a range in a Y direction. That is, under first wiring, diffusion regions are only formed in parts opposed to diffusion regions formed under the second wiring and third wiring connected to a power supply terminal or a ground terminal, and a diffusion region is not formed in a central part in an X direction. Therefore, terminal capacity of the signal terminal can be reduced without causing ESD resistance to be reduced, in an ESD protection circuit with the signal terminal.
Public/Granted literature
- US20180108650A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING AN ESD PROTECTION CIRCUIT Public/Granted day:2018-04-19
Information query
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