公开(公告)号：US20250063711A1

公开(公告)日：2025-02-20

申请号：US18939347

申请日：2024-11-06

Applicant: Socionext Inc.

Inventor： Yoshinobu YAMAGAMI

IPC: H10B10/00 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Static Random Access Memory (SRAM) cell using Complementary FET (CFET) includes the first to sixth transistors each of which is a three-dimensional transistor. The first to fourth transistors are formed at the same position as each other in the first direction in which channel portions of the first to sixth transistors extend. The fifth transistor having a node connected to the first bit line and the sixth transistor having a node connected to the second bit line are formed at the same position in the first direction as each other.

公开(公告)号：US20250029923A1

公开(公告)日：2025-01-23

申请号：US18772766

申请日：2024-07-15

Applicant: Socionext Inc.

Inventor： Masato NAKOSHI

IPC: H01L23/528 ,  H01L23/00

Abstract: A semiconductor device includes a first pad; a first wiring connected to the first pad in a first direction in a plan view; a second wiring connected to the first pad in a second direction different from the first direction in the plan view; a second pad; a third wiring connected to the second pad in the first direction in the plan view; and a fourth wiring connected to the second pad in the second direction in the plan view. The second wiring is located between the third wiring and the first pad in the second direction, and the fourth wiring is located between the first wiring and the second pad in the second direction.

公开(公告)号：US20250006635A1

公开(公告)日：2025-01-02

申请号：US18886493

申请日：2024-09-16

Applicant: Socionext Inc.

Inventor： Wenzhen WANG ,  Atsushi OKAMOTO ,  Hirotaka TAKENO

IPC: H01L23/528 ,  H01L23/522

Abstract: A semiconductor device includes a chip that includes a substrate and a first interconnection layer on a surface of the substrate; and a second interconnection layer on another surface opposite to the surface of the substrate. The second interconnection layer includes a first power line having a first power potential, a second power line having a second power potential, and a switch between the first power line and the second power line. The chip includes a first grounding line, a third power line having the second power potential, a first region having the first grounding line and the third power line, a second grounding line, a fourth power line having the first power potential, and a second region having the second grounding line and the fourth power line. In plan view, the switch is between the first region and the second region.

公开(公告)号：US20250000487A1

公开(公告)日：2025-01-02

申请号：US18882246

申请日：2024-09-11

Applicant: Socionext Inc.

Inventor： Naoto ADACHI

IPC: A61B8/00

Abstract: An ultrasonic probe includes a transducer, a self-diagnosis circuit configured to perform inspection of the transducer, and an output part configured to output information that is in accordance with a result of the inspection performed by the self-diagnosis circuit.

公开(公告)号：US20240431088A1

公开(公告)日：2024-12-26

申请号：US18825831

申请日：2024-09-05

Applicant: Socionext Inc.

Inventor： Masanobu HIROSE

IPC: H10B10/00 ,  G11C11/412 ,  G11C11/419

Abstract: A 2-port SRAM cell includes load transistors, drive transistors, access transistors, a read drive transistor, and a read access transistor. Buried interconnects corresponding to write-bit lines, respectively are formed in a buried interconnect layer so as to extend in a first direction. Interconnects corresponding to a read-word line and a write-word line, respectively are formed in an interconnect layer above the buried interconnect layer so as to extend in a second direction.

公开(公告)号：US20240420301A1

公开(公告)日：2024-12-19

申请号：US18823247

申请日：2024-09-03

Applicant: Socionext Inc.

Inventor： Nobutaka YAMAGISHI ,  Martin MAIER

IPC: G06T7/00 ,  G06T1/00 ,  G06T3/18

Abstract: A display control device includes an insertion unit configured to insert a determination image into a static region of time-series images, the static region being a region in which a pixel value does not change over time, a processing unit configured to execute warping processing on an image into which the determination image is inserted, and a determination unit configured to determine whether or not a result of a CRC computation performed on the static region of the image after the warping processing matches first reference information.

公开(公告)号：US20240395944A1

公开(公告)日：2024-11-28

申请号：US18793415

申请日：2024-08-02

Applicant: Socionext Inc.

Inventor： Hiroyuki SHIMBO

IPC: H01L29/786 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L27/118 ,  H01L27/12 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775

Abstract: Provided is a semiconductor chip including a nanowire field effect transistor (FET) and having a layout configuration effective for making manufacturing the chip easy. A semiconductor chip includes a first block including a standard cell having a nanowire FET and a second block including a nanowire FET. In the first and second blocks, nanowires extending in an X direction have an arrangement pitch in a Y direction of an integer multiple of a pitch P1. Pads have an arrangement pitch in the X direction of an integer multiple of a pitch P2.

公开(公告)号：US12142606B2

公开(公告)日：2024-11-12

申请号：US17706117

申请日：2022-03-28

Applicant: Socionext Inc.

Inventor： Junji Iwahori

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423

Abstract: A standard cell includes: a gate interconnect; a dummy gate interconnect formed to be adjacent to the gate interconnect on the right side of the gate interconnect in the figure in the X direction; a pad provided between the gate interconnect and the dummy gate interconnect; a nanosheet formed to overlap the gate interconnect as viewed in plan and connected with the pad; and a dummy nanosheet formed to overlap the dummy gate interconnect as viewed in plan and connected with the pad.

公开(公告)号：US12141936B2

公开(公告)日：2024-11-12

申请号：US17825781

申请日：2022-05-26

Applicant: Socionext Inc.

Inventor： Kazuyuki Ohhashi

IPC: G06T3/00 ,  G06T3/08 ,  G06T3/14 ,  G06T7/70

Abstract: An image processing apparatus is disclosed. The image processing apparatus includes a processor connected to a memory. The processor functions as a deformation unit. The deformation unit serves to deform a reference projection screen that is a projection screen of a surrounding image of a moving object. The reference projection screen is deformed by using position information in which detection points around the moving object are accumulated and using self-location information of the moving object.

公开(公告)号：US12119301B2

公开(公告)日：2024-10-15

申请号：US17716299

申请日：2022-04-08

Applicant: Socionext Inc.

Inventor： Wenzhen Wang ,  Atsushi Okamoto ,  Hirotaka Takeno

IPC: H01L23/528 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L23/5226

Abstract: A semiconductor device includes a chip that includes a substrate and a first interconnection layer on a surface of the substrate; and a second interconnection layer on another surface opposite to the surface of the substrate. The second interconnection layer includes a first power line having a first power potential, a second power line having a second power potential, and a switch between the first power line and the second power line. The chip includes a first grounding line, a third power line having the second power potential, a first region having the first grounding line and the third power line, a second grounding line, a fourth power line having the first power potential, and a second region having the second grounding line and the fourth power line. In plan view, the switch is between the first region and the second region.