A display processing apparatus includes a primary processing chip configured to receive a first ultra-high-definition video image and generate sub-branch primary image signals, and secondary processing chips coupled to the primary processing chip and to each other. Each of the secondary processing chips is configured to receive and process one of the sub-branch primary image signals to generate a first output image signal, receive and process an image section signal obtained from a second ultra-high-definition video image to generate a second output image signal.