Invention Grant
- Patent Title: Semiconductor device and method of manufacturing the same
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Application No.: US15700669Application Date: 2017-09-11
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Publication No.: US10141397B2Publication Date: 2018-11-27
- Inventor: Akio Ichimura , Satoshi Eguchi , Tetsuya Iida , Yuya Abiko
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Tokyo
- Agency: Mattingly & Malur, PC
- Priority: JP2015-048613 20150311
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/06 ; H01L29/78 ; H01L29/10 ; H01L29/40 ; H01L29/417
Abstract:
A super junction structure having a high aspect ratio is formed. An epitaxial layer is dividedly formed in layers using the trench fill process, and when each of the layers has been formed, trenches are formed in that layer. For example, when a first epitaxial layer has been formed, first trenches are formed in the epitaxial layer. Subsequently, when a second epitaxial layer has been formed, second trenches are formed in the epitaxial layer. Subsequently, when a third epitaxial layer has been formed, third trenches are formed in the third epitaxial layer.
Public/Granted literature
- US20180012959A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME Public/Granted day:2018-01-11
Information query
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