The present invention provides a frequency synthesizer that is switchable at a high speed and includes a few unnecessary frequency components in an output frequency signal. In a frequency synthesizer 1, a DDS 2 operates based on a clock signal to generate a reference frequency signal with a predetermined reference frequency, and clock signal supply units 41 and 42 switch the clock signals that have different clock frequencies to supply to the DDS 2. When the clock signals are switched to operate the DDS 2, the storage unit 12 stores a combination of a clock frequency fclk, a reference frequency fc, and a dividing number N in association with an output frequency fVCO of the frequency synthesizer 1 such that a spurious frequency does not exist within a predetermined frequency range and a dividing number of a variable frequency divider 302 disposed on a PLL circuit 3 is minimum. Setting units 11 and 24 read setting items stored in the storage unit 12 to set respective units.