Invention Grant
- Patent Title: Hybrid clock gating methodology for high performance cores
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Application No.: US15460127Application Date: 2017-03-15
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Publication No.: US10162922B2Publication Date: 2018-12-25
- Inventor: Kalyan Kumar Oruganti , Kailash Digari , Sandeep Nellikatte Srivatsa
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Loza & Loza, LLP/Qualcomm
- Main IPC: G06F17/50
- IPC: G06F17/50 ; H03K19/00

Abstract:
A computer-implemented method for generating a circuit design is provided according to certain aspects. The method includes determining a gating efficiency of first gate-enable logic, determining a gating efficiency of second gate-enable logic, and determining one of the first gate-enable logic and the second gate-enable logic having a greater one of the determined gating efficiencies. The method also includes placing the determined one of the first gate-enable logic and the second gate-enable logic in clock gating logic of the circuit design, and placing another one of the first gate-enable logic and the second gate-enable in data gating logic of the circuit design.
Public/Granted literature
- US20180268088A1 HYBRID CLOCK GATING METHODOLOGY FOR HIGH PERFORMANCE CORES Public/Granted day:2018-09-20
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