Invention Grant
- Patent Title: Semiconductor metrology target and manufacturing method thereof
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Application No.: US15692151Application Date: 2017-08-31
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Publication No.: US10204867B1Publication Date: 2019-02-12
- Inventor: Long-Yi Chen , Jia-Hong Chu , Hsin-Chin Lin , Hsiang-Yu Su , Yun-Heng Tseng , Kai-Hsiung Chen , Yu-Ching Wang , Po-Chung Cheng , Kuei-Shun Chen , Chi-Kang CHang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: McClure, Qualey & Rodack, LLP
- Main IPC: H01L23/544
- IPC: H01L23/544 ; H01L21/66 ; G03F7/20

Abstract:
A metrology target of a semiconductor device is provided. The metrology target includes a substrate including first and second layers. The first layer includes a first grating, a second grating, and a first dummy structure. The first dummy structure is at least formed between the first grating and the second grating. The second layer is formed over the first layer and includes a third grating and a fourth grating. The first, second, third and fourth gratings are formed based on the first spatial period. The third grating and fourth grating are placed to overlap the first grating and second grating, respectively. The first grating and the third grating are formed with a first positional offset which is along a first direction. The second grating and the fourth grating are formed with a second positional offset which is along a second direction which is opposite to the first direction.
Public/Granted literature
- US20190067203A1 SEMICONDUCTOR METROLOGY TARGET AND MANUFACTURING METHOD THEREOF Public/Granted day:2019-02-28
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