公开(公告)号：US11940737B2

公开(公告)日：2024-03-26

申请号：US17315087

申请日：2021-05-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsueh-Yi Chung ,  Yung-Cheng Chen ,  Fei-Gwo Tsai ,  Chi-Hung Liao ,  Shih-Chi Fu ,  Wei-Ti Hsu ,  Jui-Ping Chuang ,  Tzong-Sheng Chang ,  Kuei-Shun Chen ,  Meng-Wei Chen

IPC: G03F7/20 ,  G03F1/50 ,  G03F1/68 ,  G03F1/70 ,  G03F1/78 ,  G03F7/00 ,  H01L21/66

CPC classification number: G03F7/70433 ,  G03F1/50 ,  G03F1/68 ,  G03F1/70 ,  G03F1/78 ,  G03F7/20 ,  G03F7/70141 ,  G03F7/70158 ,  G03F7/70716 ,  H01L22/30

Abstract: A method includes receiving a device design layout and a scribe line design layout surrounding the device design layout. The device design layout and the scribe line design layout are rotated in different directions. An optical proximity correction (OPC) process is performed on the rotated device design layout and the rotated scribe line design layout. A reticle includes the device design layout and the scribe line design layout is formed after performing the OPC process.

公开(公告)号：US20210118674A1

公开(公告)日：2021-04-22

申请号：US17114070

申请日：2020-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Tien Shen ,  Ya-Wen Yeh ,  Wei-Liang Lin ,  Ya Chang ,  Yung-Sung Yen ,  Wei-Hao Wu ,  Li-Te Lin ,  Ru-Gun Liu ,  Kuei-Shun Chen

IPC: H01L21/027 ,  H01L21/033 ,  G03F7/09 ,  H01L21/311

Abstract: The present disclosure provides a method for semiconductor manufacturing in accordance with some embodiments. The method includes providing a substrate and a patterning layer over the substrate and forming a plurality of openings in the patterning layer. The substrate includes a plurality of features to receive a treatment process. The openings partially overlap with the features from a top view while a portion of the features remains covered by the patterning layer. Each of the openings is free of concave corners. The method further includes performing an opening expanding process to enlarge each of the openings and performing a treatment process to the features through the openings. After the opening expanding process, the openings fully overlap with the features from the top view.

公开(公告)号：US10534272B2

公开(公告)日：2020-01-14

申请号：US16127017

申请日：2018-09-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsueh-Yi Chung ,  Yung-Cheng Chen ,  Fei-Gwo Tsai ,  Chi-Hung Liao ,  Shih-Chi Fu ,  Wei-Ti Hsu ,  Jui-Ping Chuang ,  Tzong-Sheng Chang ,  Kuei-Shun Chen ,  Meng-Wei Chen

IPC: G03B27/32 ,  G03F7/20 ,  G03F1/70 ,  G03F1/78 ,  G03F1/50 ,  G03F1/68 ,  H01L21/66

Abstract: A method for exposing a wafer substrate includes forming a reticle having a device pattern. A relative orientation between the device pattern and a mask field of an exposure tool is determined based on mask field utilization. The reticle is loaded on the exposure tool. The wafer substrate is rotated based on an orientation of the device pattern. Radiation is projected through the reticle onto the rotated wafer substrate by the exposure tool, thereby imaging the device pattern onto the rotated wafer substrate.

公开(公告)号：US20190067000A1

公开(公告)日：2019-02-28

申请号：US15689172

申请日：2017-08-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Tien Shen ,  Ya-Wen Yeh ,  Wei-Liang Lin ,  Ya Hui Chang ,  Yung-Sung Yen ,  Wei-Hao Wu ,  Li-Te Lin ,  Ru-Gun Liu ,  Kuei-Shun Chen

IPC: H01L21/027 ,  G03F7/095 ,  G03F7/11 ,  H01L21/306 ,  G03F7/20 ,  H01L21/02

Abstract: The present disclosure provides a method for semiconductor manufacturing in accordance with some embodiments. The method includes providing a substrate and a patterning layer over the substrate, wherein the substrate includes a plurality of features to receive a treatment process; forming at least one opening in the patterning layer, wherein the plurality of features is partially exposed in the at least one opening; applying a directional etching to expand the at least one opening in a first direction, thereby forming at least one expanded opening; and performing the treatment process to the plurality of features through the at least one expanded opening.

公开(公告)号：US10204867B1

公开(公告)日：2019-02-12

申请号：US15692151

申请日：2017-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Long-Yi Chen ,  Jia-Hong Chu ,  Hsin-Chin Lin ,  Hsiang-Yu Su ,  Yun-Heng Tseng ,  Kai-Hsiung Chen ,  Yu-Ching Wang ,  Po-Chung Cheng ,  Kuei-Shun Chen ,  Chi-Kang CHang

IPC: H01L23/544 ,  H01L21/66 ,  G03F7/20

Abstract: A metrology target of a semiconductor device is provided. The metrology target includes a substrate including first and second layers. The first layer includes a first grating, a second grating, and a first dummy structure. The first dummy structure is at least formed between the first grating and the second grating. The second layer is formed over the first layer and includes a third grating and a fourth grating. The first, second, third and fourth gratings are formed based on the first spatial period. The third grating and fourth grating are placed to overlap the first grating and second grating, respectively. The first grating and the third grating are formed with a first positional offset which is along a first direction. The second grating and the fourth grating are formed with a second positional offset which is along a second direction which is opposite to the first direction.

公开(公告)号：US09978594B1

公开(公告)日：2018-05-22

申请号：US15352118

申请日：2016-11-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Li-Yen Lin ,  Ching-Yu Chang ,  Kuei-Shun Chen ,  Chin-Hsiang Lin

IPC: H01L21/027 ,  H01L21/311 ,  G03F7/09 ,  G03F7/004 ,  G03F7/16 ,  G03F7/038 ,  G03F7/20 ,  G03F7/32

CPC classification number: H01L21/0273 ,  G03F7/0045 ,  G03F7/038 ,  G03F7/0382 ,  G03F7/091 ,  G03F7/094 ,  G03F7/162 ,  G03F7/168 ,  G03F7/2002 ,  G03F7/322 ,  G03F7/325 ,  H01L21/02203 ,  H01L21/0332 ,  H01L21/266 ,  H01L21/3081 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/31144

Abstract: Formation methods of a semiconductor device structure are provided. The method includes forming an under layer over a substrate, forming a middle layer over the under layer, and forming a patterned upper layer over the middle layer. The patterned upper layer has a first opening exposing a portion of the middle layer. The method also includes etching the portion of the middle layer exposed by the first opening to form a second opening exposing a portion of the under layer, and etching the portion of the under layer exposed by the second opening of the middle layer. The method further includes forming pores in the middle layer before or during the etching of the portion of the under layer.

公开(公告)号：US20180096090A1

公开(公告)日：2018-04-05

申请号：US15411613

申请日：2017-01-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Lin Wu ,  Cheng-Cheng Kuo ,  Chia-Ping Chiang ,  Chih-Wei Hsu ,  Hua-Tai Lin ,  Kuei-Shun Chen ,  Yuan-Hsiang Lung ,  Yan-Tso Tsai

IPC: G06F17/50 ,  H01L21/308 ,  H01L21/306 ,  H01L21/027

CPC classification number: G06F17/5072 ,  G06F17/504 ,  G06F17/5081 ,  G06F2217/12 ,  H01L21/0274 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11807

Abstract: A method of manufacturing an integrated circuit (IC) includes receiving a layout of the IC having a first region interposed between two second regions. The layout includes a first layer having first features and second and third layer having second and third features in the first region. The second and third features collectively form cut patterns for the first features. The method further includes modifying the second and third features by a mask house tool, resulting in modified second and third features, which collectively form modified cut patterns for the first features. The modifying of the second and third features meets at least one of following conditions: total spacing between adjacent modified second (third) features is greater than total spacing between adjacent second (third) features, and total length of the modified second (third) features is smaller than total length of the second (third) features.

公开(公告)号：US10734325B2

公开(公告)日：2020-08-04

申请号：US16662970

申请日：2019-10-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Long-Yi Chen ,  Jia-Hong Chu ,  Chi-Wen Lai ,  Chia-Ching Liang ,  Kai-Hsiung Chen ,  Yu-Ching Wang ,  Po-Chung Cheng ,  Hsin-Chin Lin ,  Meng-Wei Chen ,  Kuei-Shun Chen

IPC: H01L23/544 ,  H01L21/67 ,  H01L21/66 ,  H01L21/033 ,  G03F9/00 ,  G03F7/20 ,  H01L21/768

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first overlay grating over a substrate. The method includes forming a layer over the first overlay grating. The method includes forming a second overlay grating over the layer. The second overlay grating has a third strip portion and a fourth strip portion, the third strip portion and the fourth strip portion are elongated in the first elongated axis and are spaced apart from each other, there is a second distance between a third sidewall of the third strip portion and a fourth sidewall of the fourth strip portion, the third sidewall faces away from the fourth strip portion, the fourth sidewall faces the third strip portion, the first distance is substantially equal to the second distance, and the first trench extends across the third strip portion and the fourth strip portion.

公开(公告)号：US10461037B2

公开(公告)日：2019-10-29

申请号：US15797953

申请日：2017-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Long-Yi Chen ,  Jia-Hong Chu ,  Chi-Wen Lai ,  Chia-Ching Liang ,  Kai-Hsiung Chen ,  Yu-Ching Wang ,  Po-Chung Cheng ,  Hsin-Chin Lin ,  Meng-Wei Chen ,  Kuei-Shun Chen

IPC: H01L23/544 ,  H01L21/768 ,  H01L21/67 ,  H01L21/66 ,  H01L21/033 ,  G03F9/00 ,  G03F7/20

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first overlay grating over a substrate. The first overlay grating has a first strip portion and a second strip portion. The method includes forming a first layer over the first overlay grating. The first layer has a first trench elongated in a second elongated axis, the second elongated axis is substantially perpendicular to the first elongated axis, and the first trench extends across the first strip portion and the second strip portion. The method includes forming a second overlay grating over the first layer. The second overlay grating has a third strip portion and a fourth strip portion. The third strip portion and the fourth strip portion are elongated in the first elongated axis and are spaced apart from each other.

公开(公告)号：US20190258770A1

公开(公告)日：2019-08-22

申请号：US16404326

申请日：2019-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Lin Wu ,  Cheng-Cheng Kuo ,  Chia-Ping Chiang ,  Chih-Wei Hsu ,  Hua-Tai Lin ,  Kuei-Shun Chen ,  Yuan-Hsiang Lung ,  Yan-Tso Tsai

IPC: G06F17/50 ,  H01L21/308 ,  H01L21/027 ,  H01L21/306 ,  H01L27/02 ,  H01L27/118

Abstract: A method of manufacturing an integrated circuit (IC) includes receiving a layout of the IC having a first region interposed between two second regions. The layout includes a first layer having first features and second and third layer having second and third features in the first region. The second and third features collectively form cut patterns for the first features. The method further includes modifying the second and third features by a mask house tool, resulting in modified second and third features, which collectively form modified cut patterns for the first features. The modifying of the second and third features meets at least one of following conditions: total spacing between adjacent modified second (third) features is greater than total spacing between adjacent second (third) features, and total length of the modified second (third) features is smaller than total length of the second (third) features.