Invention Grant
- Patent Title: Forming an isolation barrier in an isolator
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Application No.: US15600678Application Date: 2017-05-19
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Publication No.: US10236221B2Publication Date: 2019-03-19
- Inventor: Alan John Blennerhassett
- Applicant: Analog Devices Global
- Applicant Address: BM Hamilton
- Assignee: Analog Devices Global
- Current Assignee: Analog Devices Global
- Current Assignee Address: BM Hamilton
- Agency: Wolf, Greenfield & Sacks, P.C.
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L21/768 ; H01L21/762 ; H01L29/06 ; H01L23/522 ; H01L23/64 ; H01L49/02 ; H01L21/76 ; H01L21/8234 ; H01L23/14 ; H01G4/06

Abstract:
Integrated digital isolators comprise a first transformer coil or capacitor plate mounted on an integrated circuit substrate, and separated from a second transformer coil or capacitor plate via an electrically insulating isolation layer. The electrical isolation that is achieved is dependent upon the material and thickness of the isolation layer. In order to reduce the amount of time required for fabrication while still allowing thick isolation layers to be deployed, in examples of the disclosure a pre-formed solid layer of dielectric material is bonded to the substrate over the first transformer coil or capacitive plate. The preformed solid layer is formed from a thick layer of solid dielectric material, which is ground to the required thickness, either prior to being bonded to the circuit substrate, or thereafter. Such techniques result in a thick isolation layer that is formed more quickly and with lower outgassing risk than conventional spin-coating or deposition techniques.
Public/Granted literature
- US20180337085A1 FORMING AN ISOLATION BARRIER IN AN ISOLATOR Public/Granted day:2018-11-22
Information query
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