Invention Grant
- Patent Title: Multilevel via placement with improved yield in dual damascene interconnection
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Application No.: US15452259Application Date: 2017-03-07
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Publication No.: US10242147B2Publication Date: 2019-03-26
- Inventor: Qi-Zhong Hong
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Jacqueline J. Garner; Charles A. Brill; Frank D. Cimino
- Main IPC: H01L21/44
- IPC: H01L21/44 ; G06F17/50 ; H01L23/522 ; H01L23/528
Abstract:
A method of operating a computer system to improve via electromigration in an integrated circuit with multilevel interconnect. A method of operating a computer system to improve via electromigration in an integrated circuit with multilevel interconnect using via priority groups.
Public/Granted literature
- US20170177783A1 MULTILEVEL VIA PLACEMENT WITH IMPROVED YIELD IN DUAL DAMASCENE INTERCONNECTION Public/Granted day:2017-06-22
Information query
IPC分类:
