Invention Grant
- Patent Title: Compact via structures and method of making same
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Application No.: US14752642Application Date: 2015-06-26
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Publication No.: US10249924B2Publication Date: 2019-04-02
- Inventor: Kai Xiao , Raul Enriquez Shibayama , Gong Ouyang , Jose Diego Guillen Gonzalez , Beom-Taek Lee
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Womble Bond Dickson (US) LLP
- Main IPC: G06F3/041
- IPC: G06F3/041 ; H01P3/08 ; H05K1/02 ; H05K1/11 ; H05K3/40 ; H05K3/42 ; H01P5/02

Abstract:
Techniques and mechanisms to provide a compact arrangement of vias extending through at least a portion of a printed circuit board (PCB) or other substrate. In an embodiment, the substrate includes a dielectric material and a sidewall structure forming a hole region that extends at least partially through the dielectric material. The hole region adjoins each of a first via and a second via, and is also located between the first via and second via. In another embodiment, the first via is coupled to exchange a first signal of a differential signal pair, and the second via is coupled to exchange a second signal of the same differential signal pair.
Public/Granted literature
- US20160378215A1 COMPACT VIA STRUCTURES AND METHOD OF MAKING SAME Public/Granted day:2016-12-29
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