- Patent Title: Achieving consistent read times in multi-level non-volatile memory
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Application No.: US15803107Application Date: 2017-11-03
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Publication No.: US10254977B2Publication Date: 2019-04-09
- Inventor: Anand S. Ramalingam , Pranav Kalavade
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Jordan IP Law, LLC
- Main IPC: G11C7/00
- IPC: G11C7/00 ; G06F3/06 ; G06F12/02

Abstract:
Systems, apparatuses and methods may provide for technology that reads a lower page, one or more intermediate pages and a last page from a set of multi-level non-volatile memory (NVM) cells, wherein one or more of a lower read time associated with the lower page or a last read time associated with the last page is substantially similar to an intermediate read time associated with the one or more intermediate pages.
Public/Granted literature
- US20180188978A1 ACHIEVING CONSISTENT READ TIMES IN MULTI-LEVEL NON-VOLATILE MEMORY Public/Granted day:2018-07-05
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