Invention Grant
- Patent Title: Methods of manufacturing fin field effect transistors (FinFETs) comprising reduced gate thicknesses overlying deep trenches
-
Application No.: US15728965Application Date: 2017-10-10
-
Publication No.: US10256342B2Publication Date: 2019-04-09
- Inventor: Yong-hee Park , Young-seok Song , Ji-soo Chang , Young-chul Hwang
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR
- Assignee: Samsung Electronic Co., Ltd.
- Current Assignee: Samsung Electronic Co., Ltd.
- Current Assignee Address: KR
- Agency: Ward and Smith, P.A.
- Priority: KR10-2014-0123715 20140917
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L29/78 ; H01L27/088 ; H01L29/66 ; H01L27/092
Abstract:
An IC device includes a substrate including a device region having a fin-type active region and a deep trench region; a gate line that extends in a direction intersecting the fin-type active region; and an inter-device isolation layer that fills the deep trench region. The gate line includes a first gate portion that extends on the device region to cover the fin-type active region and has a flat upper surface at a first level and a second gate portion that extends on the deep trench region to cover the inter-device isolation layer while being integrally connected to the first gate portion and has an upper surface at a second level that is closer to the substrate than the first level.
Public/Granted literature
- US20180033890A1 METHODS OF MANUFACTURING INTEGRATED CIRCUIT DEVICES Public/Granted day:2018-02-01
Information query
IPC分类:
