Invention Grant
- Patent Title: Test method of delay circuit including delay line
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Application No.: US15344722Application Date: 2016-11-07
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Publication No.: US10256798B2Publication Date: 2019-04-09
- Inventor: Noriyuki Tokuhiro , Masazumi Maeda
- Applicant: FUJITSU LIMITED
- Applicant Address: JP Kawasaki
- Assignee: FUJITSU LIMITED
- Current Assignee: FUJITSU LIMITED
- Current Assignee Address: JP Kawasaki
- Agency: Fujitsu Patent Center
- Priority: JP2015-235659 20151202
- Main IPC: G01R31/28
- IPC: G01R31/28 ; H03K5/13 ; H03K5/133 ; H03K5/00
Abstract:
A delay circuit includes: a delay line that delays an input signal in accordance with a delay setting signal and performs output of the input signal as a delayed signal; and a logic circuit processes the input signal to the delay line and the delayed signal.
Public/Granted literature
- US20170163250A1 DELAY CIRCUIT AND TEST METHOD OF DELAY CIRCUIT Public/Granted day:2017-06-08
Information query
