Invention Grant
- Patent Title: DRAM adjacent row disturb mitigation
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Application No.: US15803710Application Date: 2017-11-03
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Publication No.: US10262717B2Publication Date: 2019-04-16
- Inventor: David Edward Fisch , William C. Plants
- Applicant: Invensas Corporation
- Applicant Address: US CA San Jose
- Assignee: Invensas Corporation
- Current Assignee: Invensas Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: G11C11/406
- IPC: G11C11/406 ; G11C11/408 ; G11C29/02 ; G11C29/06 ; G11C29/00 ; G11C29/04

Abstract:
The invention pertains to mitigation of row hammer attacks in DRAM integrated circuits. Apparatus and methods are disclosed for an embedded target row refresh (TRR) solution with modest overhead. In operation it is nearly transparent to the user. Except for enablement via the mode register and an increase in the average refresh rate on the order of half of one percent, no further user action is required. The stream of row addresses accompanying ACTIVE commands is monitored and filtered to only track addresses that occur at a dangerous rate and reject addresses that occur at less than a dangerous rate.
Public/Granted literature
- US20180114561A1 DRAM Adjacent Row Disturb Mitigation Public/Granted day:2018-04-26
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