Invention Grant
- Patent Title: Boundary spacer structure and integration
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Application No.: US15630547Application Date: 2017-06-22
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Publication No.: US10262903B2Publication Date: 2019-04-16
- Inventor: Judson R. Holt , Yi Qi , Hsien-Ching Lo , Jianwei Peng
- Applicant: GLOBALFOUNDRIES INC.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Roberts Mlotkowski Safran Cole & Calderon, P.C.
- Agent Francois Pagette; Andrew M. Calderon
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L21/02 ; H01L27/092 ; H01L29/08 ; H01L29/06

Abstract:
The present disclosure relates to semiconductor structures and, more particularly, to an N-P boundary spacer structure used with finFET devices and methods of manufacture. The method includes forming a plurality of first fin structures, forming a blocking layer between a first fin structure of the plurality of fin structures and a second fin structure of the plurality of fin structures, and forming an epitaxial material on the first fin structure, while blocking the epitaxial material from extending onto the second fin structure by at least the blocking layer formed between the first fin structure and the second fin structure.
Public/Granted literature
- US20180374759A1 BOUNDARY SPACER STRUCTURE AND INTEGRATION Public/Granted day:2018-12-27
Information query
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