Invention Grant
- Patent Title: III-V semiconductor layers, III-V semiconductor devices and methods of manufacturing thereof
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Application No.: US15397508Application Date: 2017-01-03
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Publication No.: US10263073B2Publication Date: 2019-04-16
- Inventor: Mark Van Dal , Gerben Doornbos , Matthias Passlack , Martin Christopher Holland
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: McDermott Will & Emery LLP
- Main IPC: H01L21/306
- IPC: H01L21/306 ; H01L29/06 ; H01L29/78 ; H01L29/423 ; H01L29/66 ; H01L29/775 ; H01L29/20 ; B82Y10/00 ; H01L29/10 ; H01L29/04

Abstract:
A gate-all-around field effect transistor (GAA FET) includes an InAs nano-wire as a channel layer, a gate dielectric layer wrapping the InAs nano-wire, and a gate electrode metal layer formed on the gate dielectric layer. The InAs nano-wire has first to fourth major surfaces three convex-rounded corner surfaces and one concave-rounded corner surface.
Public/Granted literature
- US20180151669A1 III-V SEMICONDUCTOR LAYERS, III-V SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF Public/Granted day:2018-05-31
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