Invention Grant
- Patent Title: Transistor with source field plates and non-overlapping gate runner layers
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Application No.: US15415995Application Date: 2017-01-26
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Publication No.: US10263085B2Publication Date: 2019-04-16
- Inventor: Hiroyuki Tomomatsu , Sameer Pendharkar , Hiroshi Yamasaki
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Andrew R. Ralston; Charles A. Brill; Frank D. Cimino
- Main IPC: H01L29/40
- IPC: H01L29/40 ; H01L29/778 ; H01L29/423 ; H01L29/20

Abstract:
A transistor device includes a field plate that extends from a source runner layer and/or a source contact layer. The field plate can be coplanar with and/or below a gate runner layer. The gate runner layer is routed away from a region directly above the gate metal layer by a gate bridge, such that the field plate can extend directly above the gate metal layer without being interfered by the gate runner layer. Coplanar with the source runner layer or the source contact layer, the field plate is positioned close to the channel region, which helps reduce its parasitic capacitance. By vertically overlapping the metal gate layer and the field plate, the disclosed HEMT device may achieve significant size efficiency without additional routings.
Public/Granted literature
- US20180190777A1 TRANSISTOR WITH SOURCE FIELD PLATES AND NON-OVERLAPPING GATE RUNNER LAYERS Public/Granted day:2018-07-05
Information query
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