Invention Grant
- Patent Title: Passive element array and printed wiring board
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Application No.: US16133736Application Date: 2018-09-18
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Publication No.: US10264674B2Publication Date: 2019-04-16
- Inventor: Keito Yonemori , Hirokazu Yazaki
- Applicant: Murata Manufacturing Co., Ltd.
- Applicant Address: JP Kyoto
- Assignee: MURATA MANUFACTURING CO., LTD.
- Current Assignee: MURATA MANUFACTURING CO., LTD.
- Current Assignee Address: JP Kyoto
- Agency: Keating & Bennett, LLP
- Priority: JP2016-081477 20160414; JP2016-093485 20160506
- Main IPC: H05K1/11
- IPC: H05K1/11 ; H05K1/16 ; H01F27/28 ; H05K1/02 ; H05K1/14 ; H05K1/18

Abstract:
A passive element array includes an element body that includes laminated base material layers, passive elements at different positions in the element body when viewed from a lamination direction of the base material layers, input/output terminals at a first main surface of the element body and connected to one end of each of the passive elements, input/output terminals at a second main surface of the element body and connected to the other end of each of the passive elements, a first ground terminal between the first input/output terminal and the input/output terminal at the first main surface, and a second ground terminal between the input/output terminal and the input/output terminal at the second main surface.
Public/Granted literature
- US20190021166A1 PASSIVE ELEMENT ARRAY AND PRINTED WIRING BOARD Public/Granted day:2019-01-17
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