Invention Grant
- Patent Title: Passive element array and printed wiring board
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Application No.: US16128573Application Date: 2018-09-12
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Publication No.: US10264676B2Publication Date: 2019-04-16
- Inventor: Hirokazu Yazaki , Keito Yonemori
- Applicant: Murata Manufacturing Co., Ltd.
- Applicant Address: JP Kyoto
- Assignee: MURATA MANUFACTURING CO., LTD.
- Current Assignee: MURATA MANUFACTURING CO., LTD.
- Current Assignee Address: JP Kyoto
- Agency: Keating & Bennett, LLP
- Priority: JP2016-081477 20160414; JP2016-093485 20160506
- Main IPC: H05K1/16
- IPC: H05K1/16 ; H05K1/11 ; H05K1/18 ; H01F27/28

Abstract:
A passive element array includes an element body including laminated base material layers, first and second passive elements arranged in the element body perpendicular or substantially perpendicular to a lamination direction of the plurality of base material layers, a pair of first input/output terminals provided at one main surface of the element body and connected to the first passive element and a pair of second input/output terminals provided at the other main surface of the element body and connected to the second passive element.
Public/Granted literature
- US20190014665A1 PASSIVE ELEMENT ARRAY AND PRINTED WIRING BOARD Public/Granted day:2019-01-10
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