Invention Grant
- Patent Title: Techniques for enforcing control flow integrity using binary translation
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Application No.: US15430652Application Date: 2017-02-13
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Publication No.: US10268819B2Publication Date: 2019-04-23
- Inventor: Koichi Yamada , Palanivelrajan Shanmugavelayutham , Sravani Konda
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Main IPC: G06F21/00
- IPC: G06F21/00 ; G06F21/54 ; G06F8/30 ; G06F8/52 ; G06F9/455

Abstract:
Various embodiments are generally directed to an apparatus, method and other techniques to determine a valid target address for a branch instruction from information stored in a relocation table, a linkage table, or both, the relocation table and the linkage table associated with a binary file and store the valid target address in a table in memory, the valid target address to validate a target address for a translated portion of a routine of the binary file.
Public/Granted literature
- US20170316201A1 TECHNIQUES FOR ENFORCING CONTROL FLOW INTEGRITY USING BINARY TRANSLATION Public/Granted day:2017-11-02
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